Datasheet

DS6329 Rev 16 11/184
STM32F20xxx List of figures
12
Figure 38. FT I/O input characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Figure 39. I/O AC characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Figure 40. Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Figure 41. I
2
C bus AC waveforms and measurement circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Figure 42. SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Figure 43. SPI timing diagram - slave mode and CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Figure 44. SPI timing diagram - master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Figure 45. I
2
S slave timing diagram (Philips protocol)
(1)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Figure 46. I
2
S master timing diagram (Philips protocol)
(1)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Figure 47. USB OTG FS timings: definition of data signal rise and fall time . . . . . . . . . . . . . . . . . . . 121
Figure 48. ULPI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Figure 49. Ethernet SMI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Figure 50. Ethernet RMII timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Figure 51. Ethernet MII timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Figure 52. ADC accuracy characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Figure 53. Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Figure 54. Power supply and reference decoupling (V
REF+
not connected to V
DDA
). . . . . . . . . . . . . 128
Figure 55. Power supply and reference decoupling (V
REF+
connected to V
DDA
). . . . . . . . . . . . . . . . 129
Figure 56. 12-bit buffered/non-buffered DAC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
Figure 57. Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms . . . . . . . . . . . . . . 133
Figure 58. Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms . . . . . . . . . . . . . . 134
Figure 59. Asynchronous multiplexed PSRAM/NOR read waveforms. . . . . . . . . . . . . . . . . . . . . . . . 135
Figure 60. Asynchronous multiplexed PSRAM/NOR write waveforms . . . . . . . . . . . . . . . . . . . . . . . 136
Figure 61. Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
Figure 62. Synchronous multiplexed PSRAM write timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
Figure 63. Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . 140
Figure 64. Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
Figure 65. PC Card/CompactFlash controller waveforms for common memory read access . . . . . . 143
Figure 66. PC Card/CompactFlash controller waveforms for common memory write access. . . . . . 143
Figure 67. PC Card/CompactFlash controller waveforms for attribute memory read access . . . . . . 144
Figure 68. PC Card/CompactFlash controller waveforms for attribute memory write access . . . . . . 145
Figure 69. PC Card/CompactFlash controller waveforms for I/O space read access . . . . . . . . . . . . 145
Figure 70. PC Card/CompactFlash controller waveforms for I/O space write access . . . . . . . . . . . . 146
Figure 71. NAND controller waveforms for read access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
Figure 72. NAND controller waveforms for write access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
Figure 73. NAND controller waveforms for common memory read access . . . . . . . . . . . . . . . . . . . . 149
Figure 74. NAND controller waveforms for common memory write access. . . . . . . . . . . . . . . . . . . . 149
Figure 75. SDIO high-speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
Figure 76. SD default mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
Figure 77. LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat package outline . . . . . . . . . . . . . . . . 152
Figure 78. LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat package
recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
Figure 79. WLCSP64+2 - 66-ball, 3.639 x 3.971 mm, 0.4 mm pitch wafer level chip scale
package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
Figure 80. WLCSP64+2 - 66-ball, 4.539 x 4.911 mm, 0.4 mm pitch wafer level chip scale
package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
Figure 81. LQFP100 - 100-pin, 14 x 14 mm low-profile quad flat package outline . . . . . . . . . . . . . . 156
Figure 82. LQFP100 - 100-pin, 14 x 14 mm low-profile quad flat
recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
Figure 83. LQFP100 marking (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
Figure 84. LQFP144 - 144-pin, 20 x 20 mm low-profile quad flat package outline . . . . . . . . . . . . . . 159
Figure 85. LQFP144 - 144-pin,20 x 20 mm low-profile quad flat package
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