Datasheet

ManualsBrandsST ManualsEmbedded Processors & ControllersMicrocontroller 32bit 128KB LQFP

This is information on a product in full production.

March 2019 DS6329 Rev 16 1/184

STM32F205xx

STM32F207xx

Arm

-based 32-bit MCU, 150 DMIPs, up to 1 MB Flash/128+4KB RAM, USB

OTG HS/FS, Ethernet, 17 TIMs, 3 ADCs, 15 comm. interfaces and camera

Datasheet - production data

Features

• Core: Arm

32-bit Cortex

-M3 CPU (120 MHz

max) with Adaptive real-time accelerator (ART

Accelerator™) allowing 0-wait state execution

performance from Flash memory, MPU,

150 DMIPS/1.25 DMIPS/MHz (Dhrystone 2.1)

• Memories

– Up to 1 Mbyte of Flash memory

– 512 bytes of OTP memory

– Up to 128 + 4 Kbytes of SRAM

– Flexible static memory controller that

supports Compact Flash, SRAM, PSRAM,

NOR and NAND memories

– LCD parallel interface, 8080/6800 modes

• Clock, reset and supply management

– From 1.8 to 3.6 V application supply + I/Os

– POR, PDR, PVD and BOR

– 4 to 26 MHz crystal oscillator

– Internal 16 MHz factory-trimmed RC

– 32 kHz oscillator for RTC with calibration

– Internal 32 kHz RC with calibration

• Low-power modes

– Sleep, Stop and Standby modes

–V

BAT

supply for RTC, 20 × 32 bit backup

registers, and optional 4 Kbytes backup

SRAM

• 3 × 12-bit, 0.5 µs ADCs with up to 24 channels

and up to 6 MSPS in triple interleaved mode

• 2 × 12-bit D/A converters

• General-purpose DMA: 16-stream controller

with centralized FIFOs and burst support

• Up to 17 timers

– Up to twelve 16-bit and two 32-bit timers,

up to 120 MHz, each with up to four

IC/OC/PWM or pulse counter and

quadrature (incremental) encoder input

• Debug mode: Serial wire debug (SWD), JTAG,

and Cortex

-M3 Embedded Trace Macrocell™

•

• Up to 140 I/O ports with interrupt capability:

– Up to 136 fast I/Os up to 60 MHz

– Up to 138 5 V-tolerant I/Os

• Up to 15 communication interfaces

– Up to three I

C interfaces (SMBus/PMBus)

– Up to four USARTs and two UARTs

(7.5 Mbit/s, ISO 7816 interface, LIN, IrDA,

modem control)

– Up to three SPIs (30 Mbit/s), two with

muxed I

S to achieve audio class accuracy

via audio PLL or external PLL

– 2 × CAN interfaces (2.0B Active)

– SDIO interface

• Advanced connectivity

– USB 2.0 full-speed device/host/OTG

controller with on-chip PHY

– USB 2.0 high-speed/full-speed

device/host/OTG controller with dedicated

DMA, on-chip full-speed PHY and ULPI

– 10/100 Ethernet MAC with dedicated DMA:

supports IEEE 1588v2 hardware, MII/RMII

• 8- to 14-bit parallel camera interface

(48 Mbyte/s max.)

• CRC calculation unit

• 96-bit unique ID

LQFP64 (10 × 10 mm)

LQFP100 (14 × 14 mm)

LQFP144 (20 × 20 mm)

LQFP176 (24 × 24 mm)

UFBGA176

(10 × 10 mm)

WLCSP64+2

(0.400 mm pitch)

&"'!

www.st.com

Downloaded from Arrow.com.

Summary of content (184 pages)

PAGE 1
STM32F205xx STM32F207xx Arm®-based 32-bit MCU, 150 DMIPs, up to 1 MB Flash/128+4KB RAM, USB OTG HS/FS, Ethernet, 17 TIMs, 3 ADCs, 15 comm. interfaces and camera Datasheet - production data Features &"'! • Core: Arm® 32-bit Cortex®-M3 CPU (120 MHz max) with Adaptive real-time accelerator (ART Accelerator™) allowing 0-wait state execution performance from Flash memory, MPU, 150 DMIPS/1.25 DMIPS/MHz (Dhrystone 2.
PAGE 2
STM32F20xxx Table 1. Device summary Reference Part numbers STM32F205xx STM32F205RB, STM32F205RC, STM32F205RE, STM32F205RF, STM32F205RG STM32F205VB, STM32F205VC, STM32F205VE, STM32F205VF, STM32F205VG STM32F205ZC, STM32F205ZE, STM32F205ZF, STM32F205ZG STM32F207xx STM32F207IC, STM32F207IE, STM32F207IF, STM32F207IG STM32F207VC, STM32F207VE, STM32F207VF, STM32F207VG STM32F207ZC, STM32F207ZE, STM32F207ZF, STM32F207ZG 2/184 Downloaded from Arrow.com.
PAGE 3
STM32F20xxx Contents Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.1 3 Full compatibility throughout the family . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.
PAGE 4
Contents STM32F20xxx 3.20.4 Independent watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 3.20.5 Window watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 3.20.6 SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 3.21 Inter-integrated circuit interface (I²C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 3.
PAGE 5
STM32F20xxx Contents 6.1.7 7 Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 6.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 6.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 6.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 6.3.2 VCAP1/VCAP2 external capacitor . . . . . . . . . . . . . . . .
PAGE 6
Contents STM32F20xxx 7.4 LQFP144 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 7.5 LQFP176 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 7.6 UFBGA176+25 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 7.7 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 8 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PAGE 7
STM32F20xxx List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. Table 43. Table 44. Table 45. Table 46. Device summary .
PAGE 8
List of tables Table 47. Table 48. Table 49. Table 50. Table 51. Table 52. Table 53. Table 54. Table 55. Table 56. Table 57. Table 58. Table 59. Table 60. Table 61. Table 62. Table 63. Table 64. Table 65. Table 66. Table 67. Table 68. Table 69. Table 70. Table 71. Table 72. Table 73. Table 74. Table 75. Table 76. Table 77. Table 78. Table 79. Table 80. Table 81. Table 82. Table 83. Table 84. Table 85. Table 86. Table 87. Table 88. Table 89. Table 90. Table 91. Table 92. 8/184 Downloaded from Arrow.com.
PAGE 9
STM32F20xxx Table 93. Table 94. Table 95. Table 96. List of tables UFBGA176+25, - 201-ball, 10 x 10 mm, 0.65 mm pitch, ultra fine pitch ball grid array package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . 166 UFBGA176+25 recommended PCB design rules (0.65 mm pitch BGA) . . . . . . . . . . . . . 167 Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 Document revision history . . . . . . . . . . . . . . . . . . .
PAGE 10
List of figures STM32F20xxx List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. 10/184 Downloaded from Arrow.com.
PAGE 11
STM32F20xxx Figure 38. Figure 39. Figure 40. Figure 41. Figure 42. Figure 43. Figure 44. Figure 45. Figure 46. Figure 47. Figure 48. Figure 49. Figure 50. Figure 51. Figure 52. Figure 53. Figure 54. Figure 55. Figure 56. Figure 57. Figure 58. Figure 59. Figure 60. Figure 61. Figure 62. Figure 63. Figure 64. Figure 65. Figure 66. Figure 67. Figure 68. Figure 69. Figure 70. Figure 71. Figure 72. Figure 73. Figure 74. Figure 75. Figure 76. Figure 77. Figure 78. Figure 79. Figure 80. Figure 81. Figure 82.
PAGE 12
List of figures Figure 86. Figure 87. Figure 88. Figure 89. Figure 90. Figure 91. 12/184 Downloaded from Arrow.com. STM32F20xxx recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 LQFP144 marking (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 LQFP176 - 176-pin, 24 x 24 mm low profile quad flat package outline . . . . . . . . . . . . . .
PAGE 13
STM32F20xxx 1 Introduction Introduction This datasheet provides the description of the STM32F205xx and STM32F207xx lines of microcontrollers, based on Arm®(a) cores. For more details on the whole STMicroelectronics STM32 family, refer to Section 2.1: Full compatibility throughout the family. The STM32F205xx and STM32F207xx datasheet must be read in conjunction with the STM32F20x/STM32F21x reference manual. They will be referred to as STM32F20x devices throughout the document.
PAGE 14
Description 2 STM32F20xxx Description The STM32F20x family is based on the high-performance Arm® Cortex®-M3 32-bit RISC core operating at a frequency of up to 120 MHz. The family incorporates high-speed embedded memories (Flash memory up to 1 Mbyte, up to 128 Kbytes of system SRAM), up to 4 Kbytes of backup SRAM, and an extensive range of enhanced I/Os and peripherals connected to two APB buses, three AHB buses and a 32-bit multi-AHB bus matrix.
PAGE 15
Downloaded from Arrow.com. DS6329 Rev 16 Yes Operating voltage Maximum CPU frequency 12-bit DAC Number of channels 16 4 16 82 1.8 V to 3.6 V(3) 120 MHz Yes 2 3 Yes No 2 Yes USB OTG HS CAN Yes 4 2 USART UART USB OTG FS 3 3/(2)(2) Yes I C 2 SPI/(I S) 2 Yes Yes WWDG No 96 (80+16) 256 IWDG 64 (48+16) 128 2 1024 2 51 768 128 (112+16) Basic 12-bit ADC Number of channels SDIO GPIOs Camera interface Comm.
PAGE 16
/184 Downloaded from Arrow.com.
PAGE 17
Downloaded from Arrow.com. CAN Maximum CPU frequency 12-bit DAC Number of channels DS6329 Rev 16 LQFP100 16 120 MHz Yes 2 LQFP144 Junction temperature: –40 to + 125 °C Ambient temperatures: –40 to +85 °C/–40 to +105 °C 1.8 V to 3.6 V(3) 24 3 Yes Yes LQFP176/ UFBGA176 24 140 STM32F207Ix 3. On devices in WLCSP64+2 package, if IRROFF is set to VDD, the supply voltage can drop to 1.
PAGE 18
Description 2.1 STM32F20xxx Full compatibility throughout the family The STM32F205xx and STM32F207xx constitute the STM32F20x family whose members are fully pin-to-pin, software and feature compatible, allowing the user to try different memory densities and peripherals for a greater degree of freedom during the development cycle. The STM32F205xx and STM32F207xx devices maintain a close compatibility with the whole STM32F10xxx family. All functional pins are pin-to-pin compatible.
PAGE 19
STM32F20xxx Description Figure 2. Compatible board design between STM32F10x and STM32F2xx for LQFP100 package ȍ UHVLVWRU RU VROGHULQJ EULGJH SUHVHQW IRU WKH 670 ) [ FRQILJXUDWLRQ QRW SUHVHQW LQ WKH 670 ) [[ FRQILJXUDWLRQ 966 7ZR ȍ UHVLVWRUV FRQQHFWHG WR 966 IRU 670 ) [ 9'' 966 RU 1& IRU 670 ) [[ /4)3 966 966 5)8 9'' 966 966 9'' 966 966 IRU 670 ) [ 9'' IRU 670 ) [[ 06 9 1. RFU = reserved for future use.
PAGE 20
Description STM32F20xxx Figure 4. STM32F20x block diagram '3 '0 8/3, &. ' ',5 673 1;7 6&/ 6'$ ,171 ,' 9%86 62) (WKHUQHW 0$& '0$ ),)2 3+< 0,, RU 50,, DV $) 0',2 DV $) '0$ ),)2 86% 27* +6 6WUHDPV '0$ ),)2 )ODVK 0E\WH 51* 65$0 .% ),)2 6 %86 65$0 365$0 125 )ODVK 3& &DUG $7$ 1$1' )ODVK 65$0 .
PAGE 21
STM32F20xxx Functional overview 3 Functional overview 3.1 Arm® Cortex®-M3 core with embedded Flash and SRAM The Arm® Cortex®-M3 processor is the latest generation of processors for embedded systems. It was developed to provide a low-cost platform that meets the needs of MCU implementation, with a reduced pin count and low-power consumption, while delivering outstanding computational performance and an advanced response to interrupts.
PAGE 22
Functional overview 3.4 STM32F20xxx Embedded Flash memory The STM32F20x devices embed a 128-bit wide Flash memory of 128 Kbytes, 256 Kbytes, 512 Kbytes, 768 Kbytes or 1 Mbyte available for storing programs and data. The devices also feature 512 bytes of OTP memory that can be used to store critical user data such as Ethernet MAC addresses or cryptographic keys. 3.
PAGE 23
STM32F20xxx Functional overview Figure 5. Multi-AHB matrix 3 3 3 3 $-!?0 3 3 53"?(3?- -!# 53" /4' %THERNET (3 %4(%2.%4?- '0 $-! $-!?-%- $-!?-%- $-!?0 3 BUS '0 $-! 3 - )#/$% - $#/$% !24 !##%, 3 $ BUS ) BUS !2#ORTEX - &LASH MEMORY - 32! +BYTE - 32! +BYTE !(" PERIPH !(" PERIPH - - - !0" !0" &3-# 3TATIC -EM#TL "US MATRIX 3 AI C 3.8 DMA controller (DMA) The devices feature two general-purpose dual-port DMAs (DMA1 and DMA2) with 8 streams each.
PAGE 24
Functional overview STM32F20xxx The DMA can be used with the main peripherals: 3.9 • SPI and I2S • I2C • USART and UART • General-purpose, basic and advanced-control timers TIMx • DAC • SDIO • Camera interface (DCMI) • ADC. Flexible static memory controller (FSMC) The FSMC is embedded in all STM32F20x devices. It has four Chip Select outputs supporting the following modes: PC Card/Compact Flash, SRAM, PSRAM, NOR Flash and NAND Flash.
PAGE 25
STM32F20xxx 3.11 Functional overview External interrupt/event controller (EXTI) The external interrupt/event controller consists of 23 edge-detector lines used to generate interrupt/event requests. Each line can be independently configured to select the trigger event (rising edge, falling edge, both) and can be masked independently. A pending register maintains the status of the interrupt requests. The EXTI can detect an external line with a pulse width shorter than the Internal APB2 clock period.
PAGE 26
Functional overview STM32F20xxx in the 0 to 70 °C temperature range using an external power supply supervisor (see Section 3.16). • VSSA, VDDA = 1.8 to 3.6 V: external analog power supplies for ADC, DAC, Reset blocks, RCs and PLL. VDDA and VSSA must be connected to VDD and VSS, respectively. • VBAT = 1.65 to 3.6 V: power supply for RTC, external clock, 32 kHz oscillator and backup registers (through power switch) when VDD is not present. Refer to Figure 19: Power supply scheme for more details. 3.
PAGE 27
STM32F20xxx Functional overview There are three power modes configured by software when the regulator is ON: • MR is used in the nominal regulation mode • LPR is used in Stop modes The LP regulator mode is configured by software when entering Stop mode. • Power-down is used in Standby mode. The Power-down mode is activated only when entering Standby mode. The regulator output is in high impedance and the kernel circuitry is powered down, inducing zero consumption.
PAGE 28
Functional overview STM32F20xxx Figure 6. Regulator OFF / internal reset ON 0OWER DOWN RESET RISEN BEFORE 6#!0? 6#!0? STABILIZATION %XTERNAL 6#!0? POWER SUPPLY SUPERVISOR !PPLICATION RESET SIGNAL OPTIONAL %XT RESET CONTROLLER ACTIVE WHEN 6#!0? 6 6$$ TO 6 0! 6$$ .234 2%'/&& 6 6#!0? )22/&& 6#!0? AI B The following conditions must be respected: • VDD must always be higher than VCAP_1 and VCAP_2 to avoid current injection between power domains.
PAGE 29
STM32F20xxx Functional overview Figure 7. Regulator OFF / internal reset OFF 6$$ 6 %XTERNAL 6$$ 6#!0? POWER SUPPLY SUPERVISOR %XT RESET CONTROLLER ACTIVE WHEN 6$$ 6 AND 6#!0? 6 0! 6$$ .234 2%'/&& )22/&& 6 6#!0? 6#!0? AI B The following conditions must be respected: • VDD must always be higher than VCAP_1 and VCAP_2 to avoid current injection between power domains (see Figure 8). • PA0 must be kept low to cover both conditions: until VCAP_1 and VCAP_2 reach 1.
PAGE 30
Functional overview STM32F20xxx Figure 8. Startup in regulator OFF: slow VDD slope, power-down reset risen after VCAP_1/VCAP_2 stabilization 9'' 3'5 9 9&$3B 9&$3B 9 9 WLPH 3$ WLHG WR 1567 1567 WLPH DL E 1. This figure is valid whatever the internal reset mode (ON or OFF). Figure 9. Startup in regulator OFF: fast VDD slope, power-down reset risen before VCAP_1/VCAP_2 stabilization 9'' 3'5 9 9&$3B 9&$3B 9 9 WLPH 3$ DVVHUWHG H[WHUQDOO\ 1567 WLPH DL
PAGE 31
STM32F20xxx 3.17 Functional overview Real-time clock (RTC), backup SRAM and backup registers The backup domain of the STM32F20x devices includes: • The real-time clock (RTC) • 4 Kbytes of backup SRAM • 20 backup registers The real-time clock (RTC) is an independent BCD timer/counter. Its main features are the following: • Dedicated registers contain the second, minute, hour (in 12/24 hour), week day, date, month, year, in BCD (binary-coded decimal) format.
PAGE 32
Functional overview STM32F20xxx and the HSE crystal oscillators are disabled. The voltage regulator can also be put either in normal or in Low-power mode. The device can be woken up from the Stop mode by any of the EXTI line. The EXTI line source can be one of the 16 external lines, the PVD output, the RTC alarm / wakeup / tamper / time stamp events, the USB OTG FS/HS wakeup or the Ethernet wakeup. • Standby mode The Standby mode is used to achieve the lowest power consumption.
PAGE 33
STM32F20xxx Functional overview Table 5. Timer feature comparison (continued) Timer type Timer General purpose Basic General purpose 3.20.
PAGE 34
Functional overview 3.20.2 STM32F20xxx General-purpose timers (TIMx) There are ten synchronizable general-purpose timers embedded in the STM32F20x devices (see Table 5 for differences). TIM2, TIM3, TIM4, TIM5 The STM32F20x include 4 full-featured general-purpose timers. TIM2 and TIM5 are 32-bit timers, and TIM3 and TIM4 are 16-bit timers. The TIM2 and TIM5 timers are based on a 32bit auto-reload up/downcounter and a 16-bit prescaler.
PAGE 35
STM32F20xxx Functional overview management. It is hardware- or software-configurable through the option bytes. The counter can be frozen in debug mode. 3.20.5 Window watchdog The window watchdog is based on a 7-bit downcounter that can be set as free-running. It can be used as a watchdog to reset the device when a problem occurs. It is clocked from the main clock. It has an early warning interrupt capability and the counter can be frozen in debug mode. 3.20.
PAGE 36
Functional overview STM32F20xxx Table 6. USART feature comparison USART Standard Modem SPI LIN irDA name features (RTS/CTS) master Max baud rate Max baud rate Smartcard in Mbit/s in Mbit/s (ISO 7816) (oversampling (oversampling by 16) by 8) APB mapping USART1 X X X X X X 1.87 7.5 APB2 (max. 60 MHz) USART2 X X X X X X 1.87 3.75 APB1 (max. 30 MHz) USART3 X X X X X X 1.87 3.75 APB1 (max. 30 MHz) UART4 X - X - X - 1.87 3.75 APB1 (max.
PAGE 37
STM32F20xxx Functional overview The interface allows data transfer at up to 48 MHz in 8-bit mode, and is compliant with the SD Memory Card Specification Version 2.0. The SDIO Card Specification Version 2.0 is also supported with two different databus modes: 1-bit (default) and 4-bit. The current version supports only one SD/SDIO/MMC4.2 card at any one time and a stack of MMC4.1 or previous. In addition to SD/SDIO/MMC, this interface is fully compliant with the CE-ATA digital protocol Rev1.1. 3.
PAGE 38
Functional overview STM32F20xxx CAN is used). The 256 bytes of SRAM which are allocated for each CAN are not shared with any other peripheral. 3.28 Universal serial bus on-the-go full-speed (OTG_FS) The devices embed an USB OTG full-speed device/host/OTG peripheral with integrated transceivers. The USB OTG FS peripheral is compliant with the USB 2.0 specification and with the OTG 1.0 specification. It has software-configurable endpoint setting and supports suspend/resume.
PAGE 39
STM32F20xxx 3.30 Functional overview Audio PLL (PLLI2S) The devices feature an additional dedicated PLL for audio I2S application. It allows to achieve error-free I2S sampling clock accuracy without compromising on the CPU performance, while using USB peripherals. The PLLI2S configuration can be modified to manage an I2S sample rate change without disabling the main PLL (PLL) used for CPU, USB and Ethernet interfaces.
PAGE 40
Functional overview 3.34 STM32F20xxx ADCs (analog-to-digital converters) Three 12-bit analog-to-digital converters are embedded and each ADC shares up to 16 external channels, performing conversions in the single-shot or scan mode. In scan mode, automatic conversion is performed on a selected group of analog inputs. Additional logic functions embedded in the ADC interface allow: • Simultaneous sample and hold • Interleaved sample and hold The ADC can be served by the DMA controller.
PAGE 41
STM32F20xxx 3.37 Functional overview Serial wire JTAG debug port (SWJ-DP) The Arm SWJ-DP interface is embedded, and is a combined JTAG and serial wire debug port that enables either a serial wire debug or a JTAG probe to be connected to the target. The JTAG TMS and TCK pins are shared with SWDIO and SWCLK, respectively, and a specific sequence on the TMS pin is used to switch between JTAG-DP and SW-DP. 3.
PAGE 42
Pinouts and pin description 4 STM32F20xxx Pinouts and pin description 6$$ 633 0" 0" "//4 0" 0" 0" 0" 0" 0$ 0# 0# 0# 0! 0! Figure 10.
PAGE 43
STM32F20xxx Pinouts and pin description 6$$ 2&5 0% 0% 0" 0" "//4 0" 0" 0" 0" 0" 0$ 0$ 0$ 0$ 0$ 0$ 0$ 0$ 0# 0# 0# 0! 0! Figure 12.
PAGE 44
Pinouts and pin description STM32F20xxx 2&5 0% 0% 0" 0" "//4 0" 0" 0" 0" 0" 0' 6$$ 633 0' 0' 0' 0' 0' 0' 0$ 0$ 6$$ 633 0$ 0$ 0$ 0$ 0$ 0$ 0# 0# 0# 0! 0! 6$$ Figure 13.
PAGE 45
STM32F20xxx Pinouts and pin description 0$2?/. 0% 0% 0" 0" "//4 0" 0" 0" 0" 0" 0' 6$$ 633 0' 0' 0' 0' 0' 0' 0$ 0$ 6$$ 633 0$ 0$ 0$ 0$ 0$ 0$ 0# 0# 0# 0! 0! 6$$ 633 0) 0) 0) 0) 0) 0) 6 $$ Figure 14.
PAGE 46
Pinouts and pin description STM32F20xxx Figure 15.
PAGE 47
STM32F20xxx Pinouts and pin description Table 8.
PAGE 48
Pinouts and pin description STM32F20xxx Table 8.
PAGE 49
STM32F20xxx Pinouts and pin description Table 8.
PAGE 50
Pinouts and pin description STM32F20xxx Table 8.
PAGE 51
STM32F20xxx Pinouts and pin description Table 8.
PAGE 52
Pinouts and pin description STM32F20xxx Table 8.
PAGE 53
STM32F20xxx Pinouts and pin description Table 8.
PAGE 54
Pinouts and pin description STM32F20xxx Table 8.
PAGE 55
STM32F20xxx Pinouts and pin description Table 8.
PAGE 56
Pinouts and pin description STM32F20xxx Table 8.
PAGE 57
STM32F20xxx Pinouts and pin description Table 8.
PAGE 58
Pinouts and pin description STM32F20xxx Table 8.
PAGE 59
STM32F20xxx Pinouts and pin description Table 9.
PAGE 60
Pinouts and pin description STM32F20xxx Table 9. FSMC pin definition (continued) FSMC Pins 60/184 Downloaded from Arrow.com.
PAGE 61
Downloaded from Arrow.com.
PAGE 62
/184 Downloaded from Arrow.com.
PAGE 63
Downloaded from Arrow.com.
PAGE 64
/184 Downloaded from Arrow.com.
PAGE 65
Downloaded from Arrow.com.
PAGE 66
/184 Downloaded from Arrow.com.
PAGE 67
STM32F20xxx 5 Memory mapping Memory mapping The memory map is shown in Figure 16. DS6329 Rev 16 67/184 183 Downloaded from Arrow.com.
PAGE 68
Memory mapping STM32F20xxx Figure 16. Memory map 2ESERVED &3-# CONTROL REGISTER X! X! &&& &3-# BANK 0# #ARD X X &&& &&&& &3-# BANK .!.$ .!.$ X X &&& &&&& &3-# BANK .!.$ .!.$ X X &&& &&&& &3-# BANK ./2 032!- X # X &&& &&&& &3-# BANK ./2 032!- X X "&& &&&& &3-# BANK ./2 032!- X&&&& &&&& X% X$&&& &&&& -BYTE BLOCK .
PAGE 69
STM32F20xxx Electrical characteristics 6 Electrical characteristics 6.1 Parameter conditions Unless otherwise specified, all voltages are referenced to VSS. 6.1.1 Minimum and maximum values Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at TA = 25 °C and TA = TAmax (given by the selected temperature range).
PAGE 70
Electrical characteristics 6.1.6 STM32F20xxx Power supply scheme Figure 19. Power supply scheme 9%$7 9 *3 , 2V ,1 î ) ,2 /RJLF .HUQHO ORJLF &38 GLJLWDO 5$0 9&$3B 9&$3B 9'' î Q) î ) /HYHO VKLIWHU 287 9'' %DFNXS FLUFXLWU\ 26& . 57& :DNHXS ORJLF %DFNXS UHJLVWHUV EDFNXS 5$0 3RZHU VZLWFK 9ROWDJH UHJXODWRU 966 )ODVK PHPRU\ 5(*2)) ,552)) 9'' 9''$ 95() Q) ) Q) ) 95() 95() $'& $QDORJ 5&V 3// 9
PAGE 71
STM32F20xxx 6.1.7 Electrical characteristics Current consumption measurement Figure 20. Current consumption measurement scheme ,''B9%$7 9%$7 ,'' 9'' 9''$ DL 6.2 Absolute maximum ratings Stresses above the absolute maximum ratings listed in Table 11, Table 12, and Table 13 may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these conditions is not implied.
PAGE 72
Electrical characteristics STM32F20xxx Table 12.
PAGE 73
STM32F20xxx Electrical characteristics Table 14. General operating conditions (continued) Symbol VDD VDDA(2) VBAT Parameter Analog operating voltage (ADC limited to 1 M samples) Analog operating voltage (ADC limited to 2 M samples) VCAP1 VCAP2 PD Max 1.8 3.6 1.8(1) 3.6 2.4 3.6 1.65 3.6 2 V ≤ VDD ≤ 3.6 V –0.3 5.5 1.7 V ≤ VDD ≤ 2 V –0.3 5.2 - - Input voltage on TTa pins - –0.3 VDD+0.
PAGE 74
Electrical characteristics STM32F20xxx Table 15. Limitations depending on the operating power supply range Operating power supply range ADC operation Maximum Flash memory access frequency (fFlashmax) VDD =1.8 to 2.1 V(2) Conversion time up to 1 Msps 16 MHz with no Flash memory wait state VDD = 2.1 to 2.4 V Conversion time up to 1 Msps 18 MHz with no Flash memory wait state Conversion time up to 2 Msps 24 MHz with no Flash memory wait state VDD = 2.4 to 2.7 V VDD = 2.7 to 3.
PAGE 75
STM32F20xxx Electrical characteristics Figure 21. Number of wait states versus fCPU and VDD range :DLW VWDWHV YV )FSX DQG 9'' UDQJH 1XPEHU RI :DLW VWDWHV WR 9 WR 9 WR 9 WR 9 )FSX 0+] AI B 1. The supply voltage can drop to 1.7 V when the device operates in the 0 to 70 °C temperature range and IRROFF is set to VDD. 6.3.
PAGE 76
Electrical characteristics 6.3.3 STM32F20xxx Operating conditions at power-up / power-down (regulator ON) Subject to general operating conditions for TA. Table 17. Operating conditions at power-up / power-down (regulator ON) Symbol tVDD 6.3.4 Parameter Min Max VDD rise time rate 20 ∞ VDD fall time rate 20 ∞ Unit µs/V Operating conditions at power-up / power-down (regulator OFF) Subject to general operating conditions for TA. Table 18.
PAGE 77
STM32F20xxx 6.3.5 Electrical characteristics Embedded reset and power control block characteristics The parameters given in Table 19 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 14. Table 19. Embedded reset and power control block characteristics Symbol Parameter VPVDhyst(1) PVD hysteresis VPOR/PDR Power-on/power-down reset threshold VBOR1 Min Typ Max Unit PLS[2:0]=000 (rising edge) 2.09 2.14 2.
PAGE 78
Electrical characteristics STM32F20xxx Table 19. Embedded reset and power control block characteristics (continued) Symbol Parameter Conditions Min Typ Max Unit VBOR2 Brownout level 2 threshold Falling edge 2.44 2.50 2.56 V Rising edge 2.53 2.59 2.63 V VBOR3 Brownout level 3 threshold Falling edge 2.75 2.83 2.88 V Rising edge 2.85 2.92 2.97 V VBORhyst(1) BOR hysteresis - - 100 - mV - 0.5 1.5 3.
PAGE 79
STM32F20xxx Electrical characteristics Typical and maximum current consumption The MCU is placed under the following conditions: • At startup, all I/O pins are configured as analog inputs by firmware. • All peripherals are disabled except if it is explicitly mentioned. • The Flash memory access time is adjusted to fHCLK frequency (0 wait state from 0 to 30 MHz, 1 wait state from 30 to 60 MHz, 2 wait states from 60 to 90 MHz and 3 wait states from 90 to 120 MHz).
PAGE 80
Electrical characteristics STM32F20xxx Table 21.
PAGE 81
STM32F20xxx Electrical characteristics Figure 23. Typical current consumption vs. temperature, Run mode, code with data processing running from RAM, and peripherals ON # )$$ 25. M! # # # # # # #05 FREQUNECY -(Z -3 6 Figure 24. Typical current consumption vs. temperature, Run mode, code with data processing running from RAM, and peripherals OFF # )$$ 25.
PAGE 82
Electrical characteristics STM32F20xxx Figure 25. Typical current consumption vs. temperature, Run mode, code with data processing running from Flash, ART accelerator OFF, peripherals ON )$$ 25. M! # # #05 FREQUNECY -(Z -3 6 Figure 26. Typical current consumption vs.
PAGE 83
STM32F20xxx Electrical characteristics Table 22. Typical and maximum current consumption in Sleep mode Max(1) Typ Symbol Parameter Conditions External clock(2), all peripherals enabled(3) IDD Supply current in Sleep mode External clock(2), all peripherals disabled fHCLK TA = 25 °C TA = 85 °C TA = 105 °C 120 MHz 38 51 61 90 MHz 30 43 53 60 MHz 20 33 43 30 MHz 11 25 35 25 MHz 8 21 31 16 MHz 6 19 29 8 MHz 3.6 17.0 27.0 4 MHz 2.4 15.4 25.3 2 MHz 1.9 14.9 24.
PAGE 84
Electrical characteristics STM32F20xxx Figure 27. Typical current consumption vs. temperature in Sleep mode, peripherals ON )$$ 3,%%0 M! # # # # # # # #05 &REQUENCY -(Z -3 6 Figure 28. Typical current consumption vs.
PAGE 85
STM32F20xxx Electrical characteristics Table 23. Typical and maximum current consumptions in Stop mode Typ Symbol Parameter Conditions Supply current in Stop mode with main regulator in Run mode IDD_STOP Max TA = 25 °C TA = 25 °C TA = 85 °C Unit TA = 105 °C Flash in Stop mode, low-speed and high-speed internal RC oscillators and high-speed oscillator OFF (no independent watchdog) 0.55 1.2 11.00 20.
PAGE 86
Electrical characteristics STM32F20xxx Table 24. Typical and maximum current consumptions in Standby mode Symbol Parameter Conditions Typ Max(1) TA = 25 °C TA = 85 °C TA = 105 °C VDD = 1.8 V VDD= 2.4 V VDD = 3.3 V 3.0 3.4 4.0 15.1 25.8 2.4 2.7 3.3 12.4 20.5 2.4 2.6 3.0 12.5 24.8 1.7 1.9 2.2 9.8 19.
PAGE 87
STM32F20xxx Electrical characteristics Table 26. Peripheral current consumption Peripheral(1) AHB1 AHB2 AHB3 Typical consumption at 25 °C GPIO A 0.45 GPIO B 0.43 GPIO C 0.46 GPIO D 0.44 GPIO E 0.44 GPIO F 0.42 GPIO G 0.44 GPIO H 0.42 GPIO I 0.43 OTG_HS + ULPI 3.64 CRC 1.17 BKPSRAM 0.21 DMA1 2.76 DMA2 2.85 ETH_MAC + ETH_MAC_TX ETH_MAC_RX ETH_MAC_PTP 2.99 OTG_FS 3.16 DCMI 0.60 FSMC 1.74 DS6329 Rev 16 Unit mA 87/184 183 Downloaded from Arrow.com.
PAGE 88
Electrical characteristics STM32F20xxx Table 26. Peripheral current consumption (continued) Peripheral(1) APB1 Typical consumption at 25 °C TIM2 0.61 TIM3 0.49 TIM4 0.54 TIM5 0.62 TIM6 0.20 TIM7 0.20 TIM12 0.36 TIM13 0.28 TIM14 0.25 USART2 0.25 USART3 0.25 UART4 0.25 UART5 0.26 I2C1 0.25 I2C2 0.25 I2C3 0.25 SPI2 0.20/0.10 SPI3 0.18/0.09 CAN1 0.31 CAN2 0.30 (2) 1.11 DAC channel 1(3) 1.11 PWR 0.15 WWDG 0.15 DAC channel 1 88/184 Downloaded from Arrow.com.
PAGE 89
STM32F20xxx Electrical characteristics Table 26. Peripheral current consumption (continued) Peripheral(1) APB2 Typical consumption at 25 °C SDIO 0.69 TIM1 1.06 TIM8 1.03 TIM9 0.58 TIM10 0.37 TIM11 0.39 (4) ADC1 2.13 ADC2(4) 2.04 (4) ADC3 2.12 SPI1 1.20 USART1 0.38 USART6 0.37 Unit mA 1. External clock is 25 MHz (HSE oscillator with 25 MHz crystal) and PLL is on. 2. EN1 bit is set in DAC_CR register. 3. EN2 bit is set in DAC_CR register. 4.
PAGE 90
Electrical characteristics 6.3.8 STM32F20xxx External clock source characteristics High-speed external user clock generated from an external source The characteristics given in Table 28 result from tests performed using an high-speed external clock source, and under ambient temperature and supply voltage conditions summarized in Table 14. Table 28.
PAGE 91
STM32F20xxx Electrical characteristics Figure 30. High-speed external clock source AC timing diagram 6(3%( 6(3%, TR (3% TF (3% T7 (3% /3#?). ), T7 (3% T 4(3% %XTERNAL CLOCK SOURCE F(3%?EXT 34- & AI Figure 31.
PAGE 92
Electrical characteristics STM32F20xxx Table 30. HSE 4-26 MHz oscillator characteristics(1) (2) Symbol fOSC_IN RF IDD gm tSU(HSE(3) Parameter Conditions Min Typ Max Unit Oscillator frequency - 4 - 26 MHz Feedback resistor - - 200 - kΩ VDD=3.3 V, ESR= 30 Ω, CL=5 pF@25 MHz - 449 - VDD=3.3 V, ESR= 30 Ω, CL=10 pF@25 MHz - 532 - Startup 5 - - mA/V VDD is stabilized - 2 - ms HSE current consumption Oscillator transconductance Startup time µA 1.
PAGE 93
STM32F20xxx Electrical characteristics Table 31. LSE oscillator characteristics (fLSE = 32.768 kHz) (1) Symbol Parameter Conditions Min Typ Max Unit RF Feedback resistor - - 18.4 - MΩ IDD LSE current consumption - - - 1 µA gm Oscillator Transconductance - 2.8 - - µA/V VDD is stabilized - 2 - s tSU(LSE)(2) startup time 1. Guaranteed by design, not tested in production. 2. tSU(LSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 32.
PAGE 94
Electrical characteristics STM32F20xxx Figure 34. ACCHSI versus temperature ŵĂǆ ĂǀŐ ϲ ŵŝŶ EŽƌŵĂůŝǌĞĚ ĚĞǀŝĂƚŝŽŶ ;йͿ ϰ Ϯ Ϭ ͲϮ Ͳϰ Ͳϲ Ͳϴ Ͳϰϱ Ͳϯϱ ͲϮϱ Ͳϭϱ Ͳϱ ϱ ϭϱ Ϯϱ ϯϱ ϰϱ ϱϱ ϲϱ ϳϱ ϴϱ ϵϱ ϭϬϱ ϭϭϱ ϭϮϱ dĞŵƉĞƌĂƚƵƌĞ ;Σ Ϳ -3 6 Low-speed internal (LSI) RC oscillator Table 33. LSI oscillator characteristics (1) Symbol fLSI(2) tsu(LSI) (3) IDD(LSI)(3) Parameter Min Typ Max Unit 17 32 47 kHz LSI oscillator startup time - 15 40 µs LSI oscillator power consumption - 0.
PAGE 95
STM32F20xxx Electrical characteristics Figure 35. ACCLSI versus temperature MAX AVG MIN .ORMALIZED DEVIATI ON 4EMPERAT URE # -3 6 6.3.10 PLL characteristics The parameters given in Table 34 and Table 35 are derived from tests performed under temperature and VDD supply voltage conditions summarized in Table 14. Table 34.
PAGE 96
Electrical characteristics STM32F20xxx Table 34.
PAGE 97
STM32F20xxx Electrical characteristics Table 35. PLLI2S (audio PLL) characteristics (continued) Symbol Parameter Conditions Min Typ Max RMS - 90 - peak to peak - ±280 - Average frequency of 12.288 MHz N=432, R=5 on 1000 samples - 90 - ps WS I2S clock jitter Cycle to cycle at 48 KHz on 1000 samples - 400 - ps IDD(PLLI2S)(4) PLLI2S power consumption on VDD VCO freq = 192 MHz VCO freq = 432 MHz 0.15 0.45 - 0.40 0.
PAGE 98
Electrical characteristics 6.3.11 STM32F20xxx PLL spread spectrum clock generation (SSCG) characteristics The spread spectrum clock generation (SSCG) feature allows to reduce electromagnetic interferences (see Table 42: EMI characteristics). It is available only on the main PLL. Table 36. SSCG parameters constraint Symbol Parameter Min Typ Max(1) Unit fMod Modulation frequency - - 10 KHz md Peak modulation depth 0.25 - 2 % - 215 MODEPER * INCSTEP - - −1 - 1.
PAGE 99
STM32F20xxx Electrical characteristics Figure 36 and Figure 37 show the main PLL output clock waveforms in center spread and down spread modes, where: F0 is fPLL_OUT nominal. Tmode is the modulation period. md is the modulation depth. Figure 36. PLL output clock waveforms in center spread mode )UHTXHQF\ 3//B287 PG ) PG WPRGH [ WPRGH 7LPH 06 9 Figure 37. PLL output clock waveforms in down spread mode )UHTXHQF\ 3//B287 ) [ PG WPRGH [ WPRGH 7LPH 06 9 6.3.
PAGE 100
Electrical characteristics STM32F20xxx Table 37. Flash memory characteristics Symbol IDD Parameter Conditions Supply current Min Typ Max Write / Erase 8-bit mode VDD = 1.8 V - 5 - Write / Erase 16-bit mode VDD = 2.1 V - 8 - Write / Erase 32-bit mode VDD = 3.3 V - 12 - Unit mA Table 38.
PAGE 101
STM32F20xxx Electrical characteristics Table 39. Flash memory programming with VPP Symbol Parameter Conditions tprog Double word programming tERASE16KB Sector (16 KB) erase time tERASE64KB Sector (64 KB) erase time tERASE128KB Sector (128 KB) erase time tME Min(1) Typ Max(1) Unit - 16 100(2) µs - 230 - - 490 - - 875 - - 6.9 - s TA = 0 to +40 °C VDD = 3.3 V VPP = 8.5 V Mass erase time ms Vprog Programming voltage - 2.7 - 3.
PAGE 102
Electrical characteristics STM32F20xxx The test results are given in Table 41. They are based on the EMS levels and classes defined in application note AN1709. Table 41. EMS characteristics Symbol Parameter Conditions Level/ Class VFESD VDD = 3.
PAGE 103
STM32F20xxx Electrical characteristics Electromagnetic Interference (EMI) The electromagnetic field emitted by the device are monitored while a simple application, executing EEMBC® code, is running. This emission test is compliant with SAE IEC61967-2 standard which specifies the test board and the pin loading. Table 42. EMI characteristics Symbol Parameter Max vs. [fHSE/fCPU] Monitored frequency band Conditions Unit 25/120 MHz VDD = 3.
PAGE 104
Electrical characteristics STM32F20xxx Static latch-up Two complementary static tests are required on six parts to assess the latch-up performance: • A supply overvoltage is applied to each power supply pin • A current injection is applied to each input, output and configurable I/O pin These tests are compliant with EIA/JESD 78A IC latch-up standard. Table 44. Electrical sensitivities Symbol LU 6.3.
PAGE 105
STM32F20xxx 6.3.16 Electrical characteristics I/O port characteristics General input/output characteristics Unless otherwise specified, the parameters given in Table 50 are derived from tests performed under the conditions summarized in Table 14: General operating conditions. All I/Os are CMOS and TTL compliant. Table 46.
PAGE 106
Electrical characteristics STM32F20xxx Table 46.
PAGE 107
STM32F20xxx Electrical characteristics Figure 38.
PAGE 108
Electrical characteristics STM32F20xxx Table 47.
PAGE 109
STM32F20xxx Electrical characteristics Table 48.
PAGE 110
Electrical characteristics STM32F20xxx Figure 39. I/O AC characteristics definition WU ,2 RXW (;7(51$/ 287387 21 &/ WI ,2 RXW 7 0D[LPXP IUHTXHQF\ LV DFKLHYHG LI WU WI 7 DQG LI WKH GXW\ F\FOH LV ZKHQ ORDGHG E\ &/ VSHFLILHG LQ WKH WDEOH ³ , 2 $& FKDUDFWHULVWLFV´ 6.3.17 DL G NRST pin characteristics The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up resistor, RPU (see Table 49).
PAGE 111
STM32F20xxx 6.3.18 Electrical characteristics TIM timer characteristics The parameters given in Table 50 and Table 51 are guaranteed by design. Refer to Section 6.3.16: I/O port characteristics for details on the input/output alternate function characteristics (output compare, input capture, external clock, PWM output). Table 50. Characteristics of TIMx connected to the APB1 domain(1) Symbol tres(TIM) Parameter Conditions Min Max Unit 1 - tTIMxCLK 16.7 - ns 1 - tTIMxCLK 33.
PAGE 112
Electrical characteristics STM32F20xxx Table 51.
PAGE 113
STM32F20xxx Electrical characteristics Table 52. I2C characteristics Symbol Standard mode I2C(1)(2) Parameter Fast mode I2C(1)(2) Unit Min Max Min Max tw(SCLL) SCL clock low time 4.7 - 1.3 - tw(SCLH) SCL clock high time 4.0 - 0.6 - tsu(SDA) SDA setup time 250 - 100 - th(SDA) SDA data hold time - 3450(3) - 900(3) tr(SDA) tr(SCL) SDA and SCL rise time - 1000 - 300 tf(SDA) tf(SCL) SDA and SCL fall time - 300 - 300 th(STA) Start condition hold time 4.0 - 0.
PAGE 114
Electrical characteristics STM32F20xxx Figure 41. I2C bus AC waveforms and measurement circuit s ''B, & s ''B, & 53 53 670 )[[ 56 6'$ ,ð& EXV 56 6&/ 67$57 5(3($7(' 67$57 67$57 WVX 67$ 6'$ WI 6'$ WU 6'$ WK 67$ WVX 6'$ WZ 672 67$ 6723 WK 6'$ WZ 6&/+ 6&/ WU 6&/ WZ 6&// WI 6&/ WVX 672 DL F 1. RS= series protection resistor. 2. RP = external pull-up resistor. 3. VDD_I2C is the I2C bus power supply. Table 53. SCL frequency (fPCLK1= 30 MHz.,VDD = 3.
PAGE 115
STM32F20xxx Electrical characteristics I2S - SPI interface characteristics Unless otherwise specified, the parameters given in Table 54 for SPI or in Table 55 for I2S are derived from tests performed under the ambient temperature, fPCLKx frequency and VDD supply voltage conditions summarized in Table 14. Refer to Section 6.3.16: I/O port characteristics for more details on the input/output alternate function characteristics (NSS, SCK, MOSI, MISO for SPI and WS, CK, SD for I2S). Table 54.
PAGE 116
Electrical characteristics STM32F20xxx Figure 42. SPI timing diagram - slave mode and CPHA = 0 NSS input tc(SCK) th(NSS) SCK Input tSU(NSS) CPHA= 0 CPOL=0 tw(SCKH) tw(SCKL) CPHA= 0 CPOL=1 tv(SO) ta(SO) MISO OUT P UT tr(SCK) tf(SCK) th(SO) MS B O UT BI T6 OUT tdis(SO) LSB OUT tsu(SI) MOSI I NPUT B I T1 IN M SB IN LSB IN th(SI) ai14134c Figure 43. SPI timing diagram - slave mode and CPHA = 1 166 LQSXW 6&. LQSXW W68 166 &3+$ &32/ &3+$ &32/ WZ 6&.+ WZ 6&.
PAGE 117
STM32F20xxx Electrical characteristics Figure 44. SPI timing diagram - master mode +LJK 166 LQSXW 6&. 2XWSXW &3+$ &32/ 6&. 2XWSXW WF 6&. &3+$ &32/ &3+$ &32/ &3+$ &32/ WVX 0, 0,62 ,13 87 WZ 6&.+ WZ 6&./ 06% ,1 WU 6&. WI 6&. %,7 ,1 /6% ,1 WK 0, 026, 287387 06% 287 WY 02 % , 7 287 /6% 287 WK 02 DL F DS6329 Rev 16 117/184 183 Downloaded from Arrow.com.
PAGE 118
Electrical characteristics STM32F20xxx Table 55. I2S characteristics Symbol Min Max 1.23 1.24 Slave 0 64FS(1) I2S clock rise and fall time Capacitive load CL = 50 pF - (2) tv(WS) (3) WS valid time Master 0.
PAGE 119
STM32F20xxx Electrical characteristics Figure 45. I2S slave timing diagram (Philips protocol)(1) CK Input tc(CK) CPOL = 0 CPOL = 1 tw(CKH) th(WS) tw(CKL) WS input tv(SD_ST) tsu(WS) SDtransmit LSB transmit(2) MSB transmit Bitn transmit tsu(SD_SR) LSB transmit th(SD_SR) LSB receive(2) SDreceive th(SD_ST) MSB receive Bitn receive LSB receive ai14881b 1. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first byte. Figure 46.
PAGE 120
Electrical characteristics STM32F20xxx USB OTG FS characteristics The USB OTG interface is USB-IF certified (Full-Speed). This interface is present in both the USB OTG HS and USB OTG FS controllers. Table 56. USB OTG FS startup time Symbol tSTARTUP(1) Parameter USB OTG FS transceiver startup time Max Unit 1 µs 1. Guaranteed by design, not tested in production. Table 57.
PAGE 121
STM32F20xxx Electrical characteristics Figure 47. USB OTG FS timings: definition of data signal rise and fall time Crossover points Differen tial data lines VCRS VS S tr tf ai14137 Table 58. USB OTG FS electrical characteristics(1) Driver characteristics Symbol tr tf trfm VCRS Parameter Rise time(2) Fall time(2) Conditions Min Max Unit CL = 50 pF 4 20 ns CL = 50 pF 4 20 ns tr/tf 90 110 % - 1.3 2.0 V Rise/fall time matching Output signal crossover voltage 1.
PAGE 122
Electrical characteristics STM32F20xxx Figure 48. ULPI timing diagram #LOCK #ONTROL )N 5,0)?$)2 5,0)?.84 T3# T(# T3$ T($ DATA )N BIT T$# T$# #ONTROL OUT 5,0)?340 T$$ DATA OUT BIT AI C Table 61. ULPI timing Value(1) Symbol Parameter Unit Min Max Control in (ULPI_DIR) setup time - 2.0 Control in (ULPI_NXT) setup time - 1.5 tHC Control in (ULPI_DIR, ULPI_NXT) hold time 0 - tSD Data in setup time - 2.
PAGE 123
STM32F20xxx Electrical characteristics Figure 49. Ethernet SMI timing diagram T-$# %4(?-$# TD -$)/ %4(?-$)/ / TSU -$)/ TH -$)/ %4(?-$)/ ) AI D Table 63. Dynamics characteristics: Ethernet MAC signals for SMI Symbol Rating Min Typ Max Unit tMDC MDC cycle time (2.
PAGE 124
Electrical characteristics STM32F20xxx Table 65 gives the list of Ethernet MAC signals for MII and Figure 50 shows the corresponding timing diagram. Figure 51. Ethernet MII timing diagram MII_RX_CLK MII_RXD[3:0] MII_RX_DV MII_RX_ER tsu(RXD) tsu(ER) tsu(DV) tih(RXD) tih(ER) tih(DV) MII_TX_CLK td(TXEN) td(TXD) MII_TX_EN MII_TXD[3:0] ai15668 Table 65. Dynamics characteristics: Ethernet MAC signals for MII Symbol Rating Min Typ Max Unit tsu(RXD) Receive data setup time 7.
PAGE 125
STM32F20xxx 6.3.20 Electrical characteristics 12-bit ADC characteristics Unless otherwise specified, the parameters given in Table 66 are derived from tests performed under the ambient temperature, fPCLK2 frequency and VDDA supply voltage conditions summarized in Table 14. Table 66. ADC characteristics Symbol Parameter Conditions Min (1) Typ Max Unit - 3.6 V VDDA Power supply - VREF+ Positive reference voltage - 1.8(1)(2) - VDDA V VDDA = 1.8(1) to 2.4 V 0.6 - 15 MHz VDDA = 2.
PAGE 126
Electrical characteristics STM32F20xxx Table 66. ADC characteristics (continued) Symbol fS(3) Parameter Sampling rate (fADC = 30 MHz) Conditions Min Typ Max Unit 12-bit resolution Single ADC - - 2 Msps 12-bit resolution Interleaved Dual ADC mode - - 3.75 Msps 12-bit resolution Interleaved Triple ADC mode - - 6 Msps IVREF+(3) ADC VREF DC current consumption in conversion mode - - 300 500 µA IVDDA(3) ADC VDDA DC current consumption in conversion mode - - 1.6 1.8 mA 1.
PAGE 127
STM32F20xxx Electrical characteristics being performed on another analog input. It is recommended to add a Schottky diode (pin to ground) to analog pins which may potentially inject negative currents. Any positive injection current within the limits specified for IINJ(PIN) and ΣIINJ(PIN) in Section 6.3.16 does not affect the ADC accuracy. Figure 52.
PAGE 128
Electrical characteristics STM32F20xxx General PCB design guidelines Power supply decoupling must be performed as shown in Figure 54 or Figure 55, depending on whether VREF+ is connected to VDDA or not. The 10 nF capacitors must be ceramic (good quality), placed as close as possible to the chip. Figure 54. Power supply and reference decoupling (VREF+ not connected to VDDA) 670 95() ) Q) 9''$ ) Q) 966$ 95() DL F 1.
PAGE 129
STM32F20xxx Electrical characteristics Figure 55. Power supply and reference decoupling (VREF+ connected to VDDA) 670 ) 95() 9''$ ) Q) 95() 966$ DL F 1. VREF+ and VREF– inputs are both available on UFBGA176 package. VREF+ is also available on all packages except for LQFP64. When VREF+ and VREF– are not available, they are internally connected to VDDA and VSSA. 6.3.21 DAC electrical characteristics Table 68.
PAGE 130
Electrical characteristics STM32F20xxx Table 68. DAC characteristics (continued) Symbol Min Typ Max Unit DAC_OUT Lower DAC_OUT voltage min(2) with buffer OFF - 0.
PAGE 131
STM32F20xxx Electrical characteristics Table 68. DAC characteristics (continued) Symbol Parameter Min Typ Max Unit Max frequency for a correct DAC_OUT change when small variation in the input code (from code i to i+1LSB) - - 1 MS/s Wakeup time from off state tWAKEUP(4) (Setting the ENx bit in the DAC Control register) - 6.5 10 µs CLOAD ≤ 50 pF, RLOAD ≥ 5 kΩ input code between lowest and highest possible ones.
PAGE 132
Electrical characteristics 6.3.23 STM32F20xxx VBAT monitoring characteristics Table 70. VBAT monitoring characteristics Symbol Parameter Min Typ Max Unit KΩ R Resistor bridge for VBAT - 50 - Q Ratio on VBAT measurement - 2 - Error on Q –1 - +1 % ADC sampling time when reading the VBAT (1 mV accuracy) 5 - - µs Er (1) TS_vbat(2)(2) 1. Guaranteed by design, not tested in production. 2. Shortest sampling time can be determined in the application by multiple iterations. 6.3.
PAGE 133
STM32F20xxx Electrical characteristics Figure 57. Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms TW .% &3-#?.% TV ./%?.% T W ./% T H .%?./% &3-#?./% &3-#?.7% TV !?.% &3-#?!; = T H !?./% !DDRESS TV ",?.% T H ",?./% &3-#?.",; = T H $ATA?.% T SU $ATA?./% TH $ATA?./% T SU $ATA?.% $ATA &3-#?$; = T V .!$6?.% TW .!$6 &3-#?.!$6 AI C 1. Mode 2/B, C and D only. In Mode 1, FSMC_NADV is not used. Table 72.
PAGE 134
Electrical characteristics STM32F20xxx Figure 58. Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms WZ 1( )60&B1([ )60&B12( WY 1:(B1( WZ 1:( W K 1(B1:( )60&B1:( WK $B1:( WY $B1( )60&B$> @ $GGUHVV WY %/B1( )60&B1%/> @ WK %/B1:( 1%/ WY 'DWDB1( WK 'DWDB1:( 'DWD )60&B'> @ W Y 1$'9B1( )60&B1$'9 WZ 1$'9 DL 1. Mode 2/B, C and D only. In Mode 1, FSMC_NADV is not used. Table 73.
PAGE 135
STM32F20xxx Electrical characteristics Figure 59. Asynchronous multiplexed PSRAM/NOR read waveforms TW .% &3-#?.% TV ./%?.% T H .%?./% &3-#?./% T W ./% &3-#?.7% TV !?.% &3-#?!; = T H !?./% !DDRESS TV ",?.% TH ",?./% &3-#?.",; = .", TH $ATA?.% TSU $ATA?.% T V !?.% &3-#? !$; = TSU $ATA?./% !DDRESS T V .!$6?.% TH $ATA?./% $ATA TH !$?.!$6 TW .!$6 &3-#?.!$6 AI B Table 74.
PAGE 136
Electrical characteristics STM32F20xxx Table 74. Asynchronous multiplexed PSRAM/NOR read timings(1)(2) (continued) Symbol Min Max Unit Data hold time after FSMC_NEx high 0 - ns th(Data_NOE) Data hold time after FSMC_NOE high 0 - ns th(Data_NE) Parameter 1. CL = 30 pF. 2. Guaranteed by characterization results, not tested in production. Figure 60.
PAGE 137
STM32F20xxx Electrical characteristics Table 75. Asynchronous multiplexed PSRAM/NOR write timings(1)(2) (continued) Symbol Parameter Min Max Unit THCLK – 0.5 - ns THCLK - 1 - ns th(A_NWE) Address hold time after FSMC_NWE high th(BL_NWE) FSMC_BL hold time after FSMC_NWE high tv(BL_NE) FSMC_NEx low to FSMC_BL valid - 0.5 ns tv(Data_NADV) FSMC_NADV high to Data valid - THCLK + 2 ns th(Data_NWE) Data hold time after FSMC_NWE high THCLK – 0.5 - ns 1. CL = 30 pF. 2.
PAGE 138
Electrical characteristics STM32F20xxx Figure 61. Synchronous multiplexed NOR/PSRAM read timings %867851 WZ &/. WZ &/. )60&B&/. 'DWD ODWHQF\ WG &/./ 1([/ W G &/./ 1([+ )60&B1([ WG &/./ 1$'9/ WG &/./ 1$'9+ )60&B1$'9 WG &/./ $,9 WG &/./ $9 )60&B$> @ WG &/./ 12(+ WG &/.+ 12(/ )60&B12( WG &/./ $',9 )60&B$'> @ WK &/.+ $'9 WVX $'9 &/.+ WVX $'9 &/.+ WG &/./ $'9 $'> @ ' WVX 1:$,79 &/.+ WK &/.+ $'9 ' WK &/.+ 1:$,79 )60&B1:$,7 :$,7&)* E :$,732/ E WVX 1:$,79 &/.
PAGE 139
STM32F20xxx Electrical characteristics Table 76. Synchronous multiplexed NOR/PSRAM read timings(1)(2) (continued) Symbol Parameter Min Max Unit tsu(ADV-CLKH) FSMC_A/D[15:0] valid data before FSMC_CLK high 5 - ns th(CLKH-ADV) FSMC_A/D[15:0] valid data after FSMC_CLK high 0 - ns 1. CL = 30 pF. 2. Guaranteed by characterization results, not tested in production. Figure 62. Synchronous multiplexed PSRAM write timings "53452. TW #,+ TW #,+ &3-#?#,+ $ATA LATENCY TD #,+, .%X, TD #,+, .
PAGE 140
Electrical characteristics STM32F20xxx Table 77. Synchronous multiplexed PSRAM write timings(1)(2) (continued) Symbol Parameter Min Max Unit td(CLKL-NWEL) FSMC_CLK low to FSMC_NWE low - 1 ns td(CLKL-NWEH) FSMC_CLK low to FSMC_NWE high 0 - ns td(CLKL-ADIV) FSMC_CLK low to FSMC_AD[15:0] invalid 0 - ns td(CLKL-DATA) FSMC_A/D[15:0] valid data after FSMC_CLK low - 2 ns td(CLKL-NBLH) FSMC_CLK low to FSMC_NBL high 0.5 - ns 1. CL = 30 pF. 2.
PAGE 141
STM32F20xxx Electrical characteristics Table 78. Synchronous non-multiplexed NOR/PSRAM read timings(1)(2) (continued) Symbol Parameter Min Max Unit td(CLKL-NADVH) FSMC_CLK low to FSMC_NADV high 4 - ns td(CLKL-AV) FSMC_CLK low to FSMC_Ax valid (x=16…25) - 0 ns td(CLKL-AIV) FSMC_CLK low to FSMC_Ax invalid (x=16…25) 3 - ns td(CLKH-NOEL) FSMC_CLK high to FSMC_NOE low - 1 ns td(CLKL-NOEH) FSMC_CLK low to FSMC_NOE high 1.
PAGE 142
Electrical characteristics STM32F20xxx Table 79.
PAGE 143
STM32F20xxx Electrical characteristics Figure 65. PC Card/CompactFlash controller waveforms for common memory read access )60&B1&( B )60&B1&( B WK 1&([ $, WY 1&([ $ )60&B$> @ WK 1&([ 15(* WK 1&([ 1,25' WK 1&([ 1,2:5 WG 15(* 1&([ WG 1,25' 1&([ )60&B15(* )60&B1,2:5 )60&B1,25' )60&B1:( WG 1&( B 12( )60&B12( WZ 12( WVX ' 12( WK 12( ' )60&B'> @ DL E 1. FSMC_NCE4_2 remains high (inactive during 8-bit access. Figure 66.
PAGE 144
Electrical characteristics STM32F20xxx Figure 67. PC Card/CompactFlash controller waveforms for attribute memory read access )60&B1&( B WY 1&( B $ WK 1&( B $, )60&B1&( B +LJK )60&B$> @ )60&B1,2:5 )60&B1,25' WG 15(* 1&( B WK 1&( B 15(* )60&B15(* )60&B1:( WG 1&( B 12( WZ 12( WG 12( 1&( B )60&B12( WVX ' 12( WK 12( ' )60&B'> @ DL E 1. Only data bits 0...7 are read (bits 8...15 are disregarded). 144/184 Downloaded from Arrow.com.
PAGE 145
STM32F20xxx Electrical characteristics Figure 68. PC Card/CompactFlash controller waveforms for attribute memory write access )60&B1&( B )60&B1&( B +LJK WY 1&( B $ WK 1&( B $, )60&B$> @ )60&B1,2:5 )60&B1,25' WG 15(* 1&( B WK 1&( B 15(* )60&B15(* WG 1&( B 1:( WZ 1:( )60&B1:( WG 1:( 1&( B )60&B12( WY 1:( ' )60&B'> @ DL E 1. Only data bits 0...7 are driven (bits 8...15 remains Hi-Z). Figure 69.
PAGE 146
Electrical characteristics STM32F20xxx Figure 70. PC Card/CompactFlash controller waveforms for I/O space write access )60&B1&( B )60&B1&( B WY 1&([ $ WK 1&( B $, )60&B$> @ )60&B15(* )60&B1:( )60&B12( )60&B1,25' WG 1&( B 1,2:5 WZ 1,2:5 )60&B1,2:5 $77[+,= WY 1,2:5 ' WK 1,2:5 ' )60&B'> @ DL F Table 80.
PAGE 147
STM32F20xxx Electrical characteristics Table 81. Switching characteristics for PC Card/CF read and write cycles in I/O space(1)(2) Symbol Parameter tw(NIOWR) FSMC_NIOWR low width tv(NIOWR-D) FSMC_NIOWR low to FSMC_D[15:0] valid th(NIOWR-D) FSMC_NIOWR high to FSMC_D[15:0] invalid Min Max Unit 8THCLK - 0.5 - ns - 5THCLK- 1 ns 8THCLK- 3 - ns td(NCE4_1-NIOWR) FSMC_NCE4_1 low to FSMC_NIOWR valid - 5THCLK+ 1.
PAGE 148
Electrical characteristics STM32F20xxx Figure 71. NAND controller waveforms for read access &3-#?.#%X !,% &3-#?! #,% &3-#?! &3-#?.7% TD !,% ./% TH ./% !,% &3-#?./% .2% TSU $ ./% TH ./% $ &3-#?$; = AI C Figure 72. NAND controller waveforms for write access )60&B1&([ $/( )60&B$ &/( )60&B$ WG $/( 1:( WK 1:( $/( )60&B1:( )60&B12( 15( WY 1:( ' WK 1:( ' )60&B'> @ AI C 148/184 Downloaded from Arrow.com.
PAGE 149
STM32F20xxx Electrical characteristics Figure 73. NAND controller waveforms for common memory read access )60&B1&([ $/( )60&B$ &/( )60&B$ WG $/( 12( WK 12( $/( )60&B1:( WZ 12( )60&B12( WVX ' 12( WK 12( ' )60&B'> @ DL F Figure 74. NAND controller waveforms for common memory write access )60&B1&([ $/( )60&B$ &/( )60&B$ WG $/( 12( WZ 1:( WK 12( $/( )60&B1:( )60&B12( WG ' 1:( WY 1:( ' WK 1:( ' )60&B'> @ DL F Table 82.
PAGE 150
Electrical characteristics STM32F20xxx Table 83.
PAGE 151
STM32F20xxx Electrical characteristics Figure 76. SD default mode #+ T/6$ T/($ $ #-$ OUTPUT AI Table 85. SD/MMC characteristics Symbol Parameter Conditions Min Max Unit fPP Clock frequency in data transfer mode CL ≤ 30 pF 0 48 MHz - SDIO_CK/fPCLK2 frequency ratio - - 8/3 - tW(CKL) Clock low time, fPP = 16 MHz CL ≤ 30 pF 32 - tW(CKH) Clock high time, fPP = 16 MHz CL ≤ 30 pF 31 - tr Clock rise time CL ≤ 30 pF - 3.
PAGE 152
Package information 7 STM32F20xxx Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark. 7.1 LQFP64 package information Figure 77.
PAGE 153
STM32F20xxx Package information Table 87. LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat package mechanical data (continued) inches(1) millimeters Symbol Min Typ Max Min Typ Max c 0.090 - 0.200 0.0035 - 0.0079 D - 12.000 - - 0.4724 - D1 - 10.000 - - 0.3937 - D3 - 7.500 - - 0.2953 - E - 12.000 - - 0.4724 - E1 - 10.000 - - 0.3937 - E3 - 7.500 - - 0.2953 - e - 0.500 - - 0.0197 - K 0° 3.5° 7° 0° 3.5° 7° L 0.450 0.600 0.750 0.0177 0.
PAGE 154
Package information 7.2 STM32F20xxx WLCSP64+2 package information Figure 79. WLCSP64+2 - 66-ball, 3.639 x 3.971 mm, 0.4 mm pitch wafer level chip scale package outline $ EDOO ORFDWLRQ ' H H H 'HWDLO $ H ( * $ ) $ $ :DIHU EDFN VLGH 6LGH YLHZ %XPS VLGH 'HWDLO $ URWDWHG E\ & $ HHH E 6HDWLQJ SODQH $ );B0(B9 1. Drawing is not to scale. Table 88. WLCSP64+2 - 66-ball, 4.539 x 4.911 mm, 0.4 mm pitch wafer level chip scale package mechanical data 154/184 Downloaded from Arrow.com.
PAGE 155
STM32F20xxx Package information Table 88. WLCSP64+2 - 66-ball, 4.539 x 4.911 mm, 0.4 mm pitch wafer level chip scale package mechanical data (continued) inches(1) millimeters Symbol Min Typ Max Min Typ Max e2 - 3.200 - - 0.1260 - F - 0.220 - - 0.0087 - G - 0.386 - - 0.0152 - aaa - - 0.100 - - 0.0039 bbb - - 0.100 - - 0.0039 ccc - - 0.100 - - 0.0039 ddd - - 0.050 - - 0.0020 eee - - 0.050 - - 0.0020 1.
PAGE 156
Package information 7.3 STM32F20xxx LQFP100 package information Figure 81. LQFP100 - 100-pin, 14 x 14 mm low-profile quad flat package outline MM C ! ! ! 3%!4).' 0,!.% # '!5'% 0,!.% $ ! + CCC # , $ , $ 0). )$%.4)&)#!4)/. % % % B E ,?-%?6 1. Drawing is not to scale. Table 90. LQPF100 - 100-pin, 14 x 14 mm low-profile quad flat package mechanical data inches(1) millimeters Symbol 156/184 Downloaded from Arrow.com.
PAGE 157
STM32F20xxx Package information Table 90. LQPF100 - 100-pin, 14 x 14 mm low-profile quad flat package mechanical data (continued) inches(1) millimeters Symbol Min Typ Max Min Typ Max D3 - 12.000 - - 0.4724 - E 15.800 16.000 16.200 0.6220 0.6299 0.6378 E1 13.800 14.000 14.200 0.5433 0.5512 0.5591 E3 - 12.000 - - 0.4724 - e - 0.500 - - 0.0197 - L 0.450 0.600 0.750 0.0177 0.0236 0.0295 L1 - 1.000 - - 0.0394 - k 0.0° 3.5° 7.0° 0.0° 3.5° 7.
PAGE 158
Package information STM32F20xxx Device marking The following figure gives an example of topside marking and pin 1 position identifier location. The printed markings may differ depending on the supply chain. Other optional marking or inset/upset marks, which depend on supply chain operations, are not indicated below. Figure 83. LQFP100 marking (package top view) 3URGXFW LGHQWLILFDWLRQ 670 ) 5HYLVLRQ FRGH 9)7 ; 'DWH FRGH < :: 3LQ LGHQWLILHU 06Y 9 1.
PAGE 159
STM32F20xxx 7.4 Package information LQFP144 package information Figure 84. LQFP144 - 144-pin, 20 x 20 mm low-profile quad flat package outline 6($7,1* 3/$1( F $ $ $ & PP *$8*( 3/$1( ' / ' . $ FFF & / ' ( 3,1 ( ( E ,'(17,),&$7,21 H $B0(B9 1. Drawing is not to scale. DS6329 Rev 16 159/184 183 Downloaded from Arrow.com.
PAGE 160
Package information STM32F20xxx Table 91. LQFP144 - 144-pin, 20 x 20 mm low-profile quad flat package mechanical data inches(1) millimeters Symbol Min Typ Max Min Typ Max A - - 1.600 - - 0.0630 A1 0.050 - 0.150 0.0020 - 0.0059 A2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.170 0.220 0.270 0.0067 0.0087 0.0106 c 0.090 - 0.200 0.0035 - 0.0079 D 21.800 22.000 22.200 0.8583 0.8661 0.8740 D1 19.800 20.000 20.200 0.7795 0.7874 0.7953 D3 - 17.500 - - 0.
PAGE 161
STM32F20xxx Package information Figure 85. LQFP144 - 144-pin,20 x 20 mm low-profile quad flat package recommended footprint DL H 1. Dimensions are expressed in millimeters. DS6329 Rev 16 161/184 183 Downloaded from Arrow.com.
PAGE 162
Package information STM32F20xxx Device marking The following figure gives an example of topside marking and pin 1 position identifier location. The printed markings may differ depending on the supply chain. Other optional marking or inset/upset marks, which depend on supply chain operations, are not indicated below. Figure 86. LQFP144 marking (package top view) 5HYLVLRQ FRGH 3URGXFW LGHQWLILFDWLRQ 670 ) =*7 'DWH FRGH < :: 3LQ LGHQWLILHU 06Y 9 1.
PAGE 163
STM32F20xxx 7.5 Package information LQFP176 package information Figure 87. LQFP176 - 176-pin, 24 x 24 mm low profile quad flat package outline C ! ! ! # 3EATING PLANE MM GAUGE PLANE K ! , ($ 0). )$%.4)&)#!4)/. , $ :% % (% E :$ B 4?-%?6 1. Drawing is not to scale. Table 92. LQFP176 - 176-pin, 24 x 24 mm low profile quad flat package mechanical data Dimensions Symbol inches(1) millimeters Min Typ Max Min Typ Max A - - 1.600 - - 0.0630 A1 0.050 - 0.150 0.
PAGE 164
Package information STM32F20xxx Table 92. LQFP176 - 176-pin, 24 x 24 mm low profile quad flat package mechanical data (continued) Dimensions Symbol inches(1) millimeters Min Typ Max Min Typ Max HD 25.900 - 26.100 1.0197 - 1.0276 ZD - 1.250 - - 0.0492 - E 23.900 - 24.100 0.9409 - 0.9488 HE 25.900 - 26.100 1.0197 - 1.0276 ZE - 1.250 - - 0.0492 - e - 0.500 - - 0.0197 - 0.450 - 0.750 0.0177 - 0.0295 L1 - 1.000 - - 0.
PAGE 165
STM32F20xxx Package information Figure 88. LQFP176 - 176-pin, 24 x 24 mm low profile quad flat package recommended footprint 4?&0?6 1. Dimensions are expressed in millimeters. DS6329 Rev 16 165/184 183 Downloaded from Arrow.com.
PAGE 166
Package information 7.6 STM32F20xxx UFBGA176+25 package information Figure 89. UFBGA176+25 - 201-ball, 10 x 10 mm, 0.65 mm pitch, ultra fine pitch ball grid array package outline & ^ĞĂƚŝŶŐ ƉůĂŶĞ ϰ ĚĚĚ Ϯ $ ϭ ď Ğ $ EDOO LGHQWLILHU ( $ EDOO LQGH[ DUHD $ ' Ğ Z ϭϱ ϭ KddKD s/ t E EDOOV dKW s/ t HHH 0 & $ III 0 & $ ( B0(B9 1. Drawing is not to scale. Table 93. UFBGA176+25, - 201-ball, 10 x 10 mm, 0.
PAGE 167
STM32F20xxx Package information Table 93. UFBGA176+25, - 201-ball, 10 x 10 mm, 0.65 mm pitch, ultra fine pitch ball grid array package mechanical data (continued) inches(1) millimeters Symbol Min Typ Max Min Typ Max eee - - 0.150 - - 0.0059 fff - - 0.050 - - 0.0020 1. Values in inches are converted from mm and rounded to 4 decimal digits. Figure 90. UFBGA176+25 - 201-ball, 10 x 10 mm, 0.
PAGE 168
Package information STM32F20xxx Device marking The following figure gives an example of topside marking and ball A1 position identifier location. The printed markings may differ depending on the supply chain. Other optional marking or inset/upset marks, which depend on supply chain operations, are not indicated below. Figure 91. UFBGA176+25 marking (package top view) 5HYLVLRQ FRGH 5 3URGXFW LGHQWLILFDWLRQ 670 ) ,*+ 'DWH FRGH %DOO $ LGHQWLILHU 06 9 1.
PAGE 169
STM32F20xxx 7.7 Package information Thermal characteristics The maximum chip-junction temperature, TJ max, in degrees Celsius, may be calculated using the following equation: TJ max = TA max + (PD max x ΘJA) Where: • TA max is the maximum ambient temperature in ° C, • ΘJA is the package junction-to-ambient thermal resistance, in ° C/W, • PD max is the sum of PINT max and PI/O max (PD max = PINT max + PI/Omax), • PINT max is the product of IDD and VDD, expressed in Watts.
PAGE 170
Ordering information 8 STM32F20xxx Ordering information Example: STM32 F 205 R E T 6 V xxx Device family STM32 = Arm-based 32-bit microcontroller Product type F = general-purpose Device subfamily 205 = STM32F20x, connectivity 207= STM32F20x, connectivity, camera interface, Ethernet Pin count R = 64 pins or 66 pins(1) V = 100 pins Z = 144 pins I = 176 pins Flash memory size B = 128 Kbytes of Flash memory C = 256 Kbytes of Flash memory E = 512 Kbytes of Flash memory F = 768 Kbytes of Flash memory G
PAGE 171
STM32F20xxx 9 Revision history Revision history Table 96. Document revision history Date Revision 05-Jun-2009 1 Initial release. 2 Document status promoted from Target specification to Preliminary data. In Table 8: STM32F20x pin and ball definitions: – Note 4 updated – VDD_SA and VDD_3 pins inverted (Figure 12: STM32F20x LQFP100 pinout, Figure 13: STM32F20x LQFP144 pinout and Figure 14: STM32F20x LQFP176 pinout corrected accordingly).
PAGE 172
Revision history STM32F20xxx Table 96. Document revision history (continued) Date 13-Jul-2010 172/184 Downloaded from Arrow.com. Revision Changes Added USB OTG_FS features in Section 3.28: Universal serial bus onthe-go full-speed (OTG_FS). Updated VCAP_1 and VCAP_2 capacitor value to 2.2 µF in Figure 19: Power supply scheme. Removed DAC, modified ADC limitations, and updated I/O compensation for 1.8 to 2.1 V range in Table 15: Limitations depending on the operating power supply range.
PAGE 173
STM32F20xxx Revision history Table 96. Document revision history (continued) Date 25-Nov-2010 Revision Changes 5 Update I/Os in Section : Features. Added WLCSP64+2 package. Added note 1 related to LQFP176 on cover page. Added trademark for ART accelerator. Updated Section 3.2: Adaptive real-time memory accelerator (ART Accelerator™). Updated Figure 5: Multi-AHB matrix. Added case of BOR inactivation using IRROFF on WLCSP devices in Section 3.15: Power supply supervisor. Reworked Section 3.
PAGE 174
Revision history STM32F20xxx Table 96. Document revision history (continued) Date 22-Apr-2011 174/184 Downloaded from Arrow.com. Revision Changes 6 Changed datasheet status to “Full Datasheet”. Introduced concept of SRAM1 and SRAM2. LQFP176 package now in production and offered only for 256 Kbyte and 1 Mbyte devices. Availability of WLCSP64+2 package limited to 512 Kbyte and 1 Mbyte devices.
PAGE 175
STM32F20xxx Revision history Table 96. Document revision history (continued) Date 22-Apr-2011 Revision Changes Updated Typical and maximum current consumption conditions, as well as Table 21: Typical and maximum current consumption in Run mode, code with data processing running from Flash memory (ART accelerator disabled) and Table 20: Typical and maximum current consumption in Run mode, code with data processing running from Flash memory (ART accelerator enabled) or RAM.
PAGE 176
Revision history STM32F20xxx Table 96. Document revision history (continued) Date 22-Apr-2011 176/184 Downloaded from Arrow.com. Revision Changes Changed tw(SCKH) to tw(SCLH), tw(SCKL) to tw(SCLL), tr(SCK) to tr(SCL), and tf(SCK) to tf(SCL) in Table 52: I2C characteristics and in Figure 41: I2C bus AC waveforms and measurement circuit. Added Table 57: USB OTG FS DC electrical characteristics and updated Table 58: USB OTG FS electrical characteristics.
PAGE 177
STM32F20xxx Revision history Table 96. Document revision history (continued) Date 14-Jun-2011 20-Dec-2011 Revision Changes 7 Added SDIO in Table 2: STM32F205xx features and peripheral counts. Updated VIN for 5V tolerant pins in Table 11: Voltage characteristics. Updated jitter parameters description in Table 34: Main PLL characteristics. Remove jitter values for system clock in Table 35: PLLI2S (audio PLL) characteristics. Updated Table 42: EMI characteristics.
PAGE 178
Revision history STM32F20xxx Table 96. Document revision history (continued) Date Revision Changes Added maximum power consumption at TA=25 °C in Table 23: Typical and maximum current consumptions in Stop mode. Updated md minimum value in Table 36: SSCG parameters constraint. Added examples in Section 6.3.11: PLL spread spectrum clock generation (SSCG) characteristics. Updated Table 54: SPI characteristics and Table 55: I2S characteristics.
PAGE 179
STM32F20xxx Revision history Table 96. Document revision history (continued) Date 24-Apr-2012 Revision Changes Removed support of I2C for OTG PHY in Section 3.29: Universal serial bus on-the-go high-speed (OTG_HS). Removed OTG_HS_SCL, OTG_HS_SDA, OTG_FS_INTN in Table 8: STM32F20x pin and ball definitions and Table 10: Alternate function mapping. Renamed PH10 alternate function into TIM5_CH1 in Table 10: Alternate function mapping. Added Table 9: FSMC pin definition.
PAGE 180
Revision history STM32F20xxx Table 96. Document revision history (continued) Date 29-Oct-2012 180/184 Downloaded from Arrow.com. Revision Changes 10 Changed minimum supply voltage from 1.65 to 1.8 V. Updated number of AHB buses in Section 2: Description and Section 3.12: Clocks and startup. Removed Figure 4. Compatible board design between STM32F10xx and STM32F2xx for LQFP176 package. Updated Note 2 below Figure 4: STM32F20x block diagram.
PAGE 181
STM32F20xxx Revision history Table 96. Document revision history (continued) Date 29-Oct-2012 04-Nov-2013 Revision Changes Replaced td(CLKL-NOEL) by td(CLKH-NOEL) in Table 76: Synchronous multiplexed NOR/PSRAM read timings, Table 78: Synchronous nonmultiplexed NOR/PSRAM read timings, Figure 61: Synchronous multiplexed NOR/PSRAM read timings and Figure 63: Synchronous non-multiplexed NOR/PSRAM read timings. 10 (continued) Added Figure 87: LQFP176 recommended footprint.
PAGE 182
Revision history STM32F20xxx Table 96. Document revision history (continued) Date Revision Changes Removed note applying to VPOR/PDR minimum value in Table 19: Embedded reset and power control block characteristics. Updated notes related to CL1 and CL2 in Section : Low-speed external clock generated from a crystal/ceramic resonator. Updated conditions in Table 41: EMS characteristics. Updated Table 42: EMI characteristics. Updated VIL, VIH and VHys in Table 46: I/O static characteristics.
PAGE 183
STM32F20xxx Revision history Table 96. Document revision history (continued) Date 24-Jun-2016 11-Aug-2016 29-Mar-2019 Revision Changes 14 Updated figures 1, 2 and 3 in Section 2.1: Full compatibility throughout the family. Updated Device marking and Figure 83 in Section 7.3: LQFP100 package information. Updated Device marking and Figure 86 in Section 7.4: LQFP144 package information. Updated Section 7.6: UFBGA176+25 package information with introduction of Device marking and Figure 91.
PAGE 184
STM32F20xxx IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement.