Datasheet

Electrical characteristics STM32F103xF, STM32F103xG
114/136 DocID16554 Rev 4
INL
(2)
Integral non linearity
(difference between
measured value at Code i
and the value at Code i on a
line drawn between Code 0
and last Code 1023)
-- ±1LSB
Given for the DAC in 10-bit
configuration
-- ±4LSB
Given for the DAC in 12-bit
configuration
Offset
(2)
Offset error
(difference between
measured value at Code
(0x800) and the ideal value =
V
REF+
/2)
-- ±10mV
-- ±3LSB
Given for the DAC in 10-bit at V
REF+
= 3.6 V
-- ±12LSB
Given for the DAC in 12-bit at V
REF+
= 3.6 V
Gain
error
(2)
Gain error - - ±0.5 %
Given for the DAC in 12bit
configuration
t
SETTLING
(2)
Settling time (full scale: for a
10-bit input code transition
between the lowest and the
highest input codes when
DAC_OUT reaches final
value ±1LSB
-3 4 µsC
LOAD
≤ 50 pF, R
LOAD
≥ 5 kΩ
Update
rate
(2)
Max frequency for a correct
DAC_OUT change when
small variation in the input
code (from code i to i+1LSB)
-- 1MS/sC
LOAD
≤ 50 pF, R
LOAD
≥ 5 kΩ
t
WAKEUP
(2)
Wakeup time from off state
(Setting the ENx bit in the
DAC Control register)
- 6.5 10 µs
C
LOAD
≤ 50 pF, R
LOAD
≥ 5 kΩ
input code between lowest and
highest possible ones.
PSRR+
(1)
Power supply rejection ratio
(to V
DDA
) (static DC
measurement
- –67 –40 dB No R
LOAD
, C
LOAD
= 50 pF
1. Guaranteed by design, not tested in production.
2. The quiescent mode corresponds to a state where the DAC maintains a stable output level to ensure that no dynamic
consumption occurs.
3. Preliminary values.
Table 66. DAC characteristics (continued)
Symbol Parameter Min Typ Max Unit Comments
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