Datasheet

DocID16554 Rev 4 111/136
STM32F103xF, STM32F103xG Electrical characteristics
132
Figure 56. Typical connection diagram using the ADC
1. Refer to Table 62 for the values of R
AIN
, R
ADC
and C
ADC
.
2. C
parasitic
represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the
pad capacitance (roughly 7 pF). A high C
parasitic
value will downgrade conversion accuracy. To remedy
this, f
ADC
should be reduced.
General PCB design guidelines
Power supply decoupling should be performed as shown in Figure 57 or Figure 58,
depending on whether V
REF+
is connected to V
DDA
or not. The 10 nF capacitors should be
ceramic (good quality). They should be placed them as close as possible to the chip.
Figure 57. Power supply and reference decoupling (V
REF+
not connected to V
DDA
)
1. V
REF+
and V
REF–
inputs are available only on 100-pin packages.
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