Datasheet

ManualsBrandsST ManualsEmbedded Processors & ControllersMicrocontroller 32bit 1MB LQFP

This is information on a product in full production.

May 2015 DocID16554 Rev 4 1/136

STM32F103xF STM32F103xG

XL-density performance line ARM®-based 32-bit MCU with 768 KB

to 1 MB Flash, USB, CAN, 17 timers, 3 ADCs, 13 com. interfaces

Datasheet − production data

Features

• Core: ARM

32-bit Cortex

-M3 CPU with MPU

– 72 MHz maximum frequency,

1.25 DMIPS/MHz (Dhrystone 2.1)

performance at 0 wait state memory

access

– Single-cycle multiplication and hardware

division

• Memories

– 768 Kbytes to 1 Mbyte of Flash memory

– 96 Kbytes of SRAM

– Flexible static memory controller with 4

Chip Select. Supports Compact Flash,

SRAM, PSRAM, NOR and NAND

memories

– LCD parallel interface, 8080/6800 modes

• Clock, reset and supply management

– 2.0 to 3.6 V application supply and I/Os

– POR, PDR, and programmable voltage

detector (PVD)

– 4-to-16 MHz crystal oscillator

– Internal 8 MHz factory-trimmed RC

– Internal 40 kHz RC with calibration

– 32 kHz oscillator for RTC with calibration

• Low power

– Sleep, Stop and Standby modes

–V

BAT

supply for RTC and backup registers

• 3 × 12-bit, 1 µs A/D converters (up to 21

channels)

– Conversion range: 0 to 3.6 V

– Triple-sample and hold capability

– Temperature sensor

• 2 × 12-bit D/A converters

• DMA: 12-channel DMA controller

– Supported peripherals: timers, ADCs, DAC,

SDIO, I

Ss, SPIs, I

Cs and USARTs

• Debug mode

– Serial wire debug (SWD) & JTAG

interfaces

–Cortex

-M3 Embedded Trace Macrocell™

• Up to 112 fast I/O ports

– 51/80/112 I/Os, all mappable on 16

external interrupt vectors and almost all

5 V-tolerant

• Up to 17 timers

– Up to ten 16-bit timers, each with up to 4

IC/OC/PWM or pulse counter and

quadrature (incremental) encoder input

– 2 × 16-bit motor control PWM timers with

dead-time generation and emergency stop

– 2 × watchdog timers (Independent and

Window)

– SysTick timer: a 24-bit downcounter

– 2 × 16-bit basic timers to drive the DAC

• Up to 13 communication interfaces

– Up to 2 × I

C interfaces (SMBus/PMBus)

– Up to 5 USARTs (ISO 7816 interface, LIN,

IrDA capability, modem control)

– Up to 3 SPIs (18 Mbit/s), 2 with I

interface multiplexed

– CAN interface (2.0B Active)

– USB 2.0 full speed interface

– SDIO interface

• CRC calculation unit, 96-bit unique ID

• ECOPACK

packages

Table 1. Device summary

Reference Part number

STM32F103xF STM32F103RF STM32F103VF STM32F103ZF

STM32F103xG STM32F103RG STM32F103VG STM32F103ZG

&"'!

LQFP64 10 × 10 mm,

LQFP100 14 × 14 mm,

LQFP144 20 × 20 mm

LFBGA144 10 × 10 mm

www.st.com

Downloaded from Arrow.com.

Summary of content (136 pages)

PAGE 1
STM32F103xF STM32F103xG XL-density performance line ARM®-based 32-bit MCU with 768 KB to 1 MB Flash, USB, CAN, 17 timers, 3 ADCs, 13 com. interfaces Datasheet − production data Features &"'! ® ® • Core: ARM 32-bit Cortex -M3 CPU with MPU – 72 MHz maximum frequency, 1.25 DMIPS/MHz (Dhrystone 2.
PAGE 2
Contents STM32F103xF, STM32F103xG Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2/136 Downloaded from Arrow.com. 2.1 Device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 2.2 Full compatibility throughout the family . . . . . . . . . . . . . . . . . . . . .
PAGE 3
STM32F103xF, STM32F103xG Contents 2.3.29 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 2.3.30 Serial wire JTAG debug port (SWJ-DP) . . . . . . . . . . . . . . . . . . . . . . . . . 24 2.3.31 Embedded Trace Macrocell™ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3 Pinouts and pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 4 Memory mapping . . . . . . . . . . . . . . . . . . . . . .
PAGE 4
Contents 6 STM32F103xF, STM32F103xG 5.3.19 12-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 5.3.20 DAC electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 5.3.21 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 6.1 LFBGA144 package information . . . . . . . . . . .
PAGE 5
STM32F103xF, STM32F103xG List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. Table 43. Device summary . . . . . . . . .
PAGE 6
List of tables Table 44. Table 45. Table 46. Table 47. Table 48. Table 49. Table 50. Table 51. Table 52. Table 53. Table 54. Table 55. Table 56. Table 57. Table 58. Table 59. Table 60. Table 61. Table 62. Table 63. Table 64. Table 65. Table 66. Table 67. Table 68. Table 69. Table 70. Table 71. Table 72. Table 73. 6/136 Downloaded from Arrow.com. STM32F103xF, STM32F103xG EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PAGE 7
STM32F103xF, STM32F103xG List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Figure 38. Figure 39. Figure 40.
PAGE 8
List of figures Figure 41. Figure 42. Figure 43. Figure 44. Figure 45. Figure 46. Figure 47. Figure 48. Figure 49. Figure 50. Figure 51. Figure 52. Figure 53. Figure 54. Figure 55. Figure 56. Figure 57. Figure 58. Figure 59. Figure 60. Figure 61. Figure 62. Figure 63. Figure 64. Figure 65. Figure 66. Figure 67. Figure 68. Figure 69. Figure 70. Figure 71. 8/136 Downloaded from Arrow.com. STM32F103xF, STM32F103xG Standard I/O input characteristics - TTL port . . . . . . . . . . . . . . . . . . . . . . . .
PAGE 9
STM32F103xF, STM32F103xG 1 Introduction Introduction This datasheet provides the ordering information and mechanical device characteristics of the STM32F103xF and STM32F103xG XL-density performance line microcontrollers. For more details on the whole STMicroelectronics STM32F103xF/G family, please refer to Section 2.2: Full compatibility throughout the family. The XL-density STM32F103xF/G datasheet should be read in conjunction with the STM32F10xxx reference manual.
PAGE 10
Description 2 STM32F103xF, STM32F103xG Description The STM32F103xF and STM32F103xG performance line family incorporates the highperformance ARM® Cortex®-M3 32-bit RISC core operating at a 72 MHz frequency, highspeed embedded memories (Flash memory up to 1 Mbyte and SRAM up to 96 Kbytes), and an extensive range of enhanced I/Os and peripherals connected to two APB buses.
PAGE 11
STM32F103xF, STM32F103xG 2.1 Description Device overview The STM32F103xF/G XL-density performance line family offers devices in four different package types: from 64 pins to 144 pins. Depending on the device chosen, different sets of peripherals are included, the description below gives an overview of the complete range of peripherals proposed in this family. Figure 1 shows the general block diagram of the device family. Table 2.
PAGE 12
Description STM32F103xF, STM32F103xG 1-7567 -7', -7&. 6:&/. -706 6:'$7 -7'2 DV $) 73,8 (70 6:-7$* 7UDFH 7ULJ ,E X V )ODVK .% &RUWH[ 0 &38 )PD[ 0+] 19,& 'EXV 92/7 5(* 9 72 9 ELW 5& +6 65$0 .E\WH 325 6833/< 5HVHW 683(59,6,21 ,QW 325 3'5 39' #9'' ;7$/ 26& 0+] 5& /6 FKDQQHOV ,:'* *3 '0$ 6WDQGE\ LQWHUIDFH 5HVHW FORFN FRQWUROOHU 1567 9''$ 966$ #9''$ 3// FKDQQHOV 9'' WR 9 966 #9'' #9''$ %XV PDWUL[ *3 '0$ 3&/. 3&/. 3&/. +&/. )&/.
PAGE 13
STM32F103xF, STM32F103xG Description Figure 2. Clock tree )/,7)&/. WR )ODVK SURJUDPPLQJ LQWHUIDFH 86% 3UHVFDOHU 86%&/. WR 86% LQWHUIDFH 0+] , 6 &/. 3HULSKHUDO FORFN HQDEOH 0+] +6, 5& , 6 &/. 6: 3//08/ +6, [ [ [ [ 3// 6<6&/. $+% 3UHVFDOHU 0+] PD[ 3//&/. $3% 3UHVFDOHU $3% 3UHVFDOHU WR 57& /6( 57&&/. WR ,QGHSHQGHQW :DWFKGRJ ,:'* /6, $'& 3UHVFDOHU 3&/.
PAGE 14
Description 2.2 STM32F103xF, STM32F103xG Full compatibility throughout the family The STM32F103xF/G is a complete family whose members are fully pin-to-pin, software and feature compatible.
PAGE 15
STM32F103xF, STM32F103xG Description 2.3 Overview 2.3.1 ARM® Cortex®-M3 core with embedded Flash and SRAM The ARM Cortex®-M3 processor is the latest generation of ARM processors for embedded systems. It has been developed to provide a low-cost platform that meets the needs of MCU implementation, with a reduced pin count and low-power consumption, while delivering outstanding computational performance and an advanced system response to interrupts.
PAGE 16
Description 2.3.5 STM32F103xF, STM32F103xG Embedded SRAM 96 Kbytes of embedded SRAM accessed (read/write) at CPU clock speed with 0 wait states. 2.3.6 FSMC (flexible static memory controller) The FSMC is embedded in the STM32F103xF and STM32F103xG performance line family. It has four Chip Select outputs supporting the following modes: PC Card/Compact Flash, SRAM, PSRAM, NOR and NAND. Functionality overview: 2.3.
PAGE 17
STM32F103xF, STM32F103xG 2.3.10 Description Clocks and startup System clock selection is performed on startup, however the internal RC 8 MHz oscillator is selected as default CPU clock on reset. An external 4-16 MHz clock can be selected, in which case it is monitored for failure. If failure is detected, the system automatically switches back to the internal RC oscillator. A software interrupt is generated if enabled.
PAGE 18
Description 2.3.14 STM32F103xF, STM32F103xG Voltage regulator The regulator has three operation modes: main (MR), low-power (LPR) and power down. • MR is used in the nominal regulation mode (Run) • LPR is used in the Stop modes. • Power down is used in Standby mode: the regulator output is in high impedance: the kernel circuitry is powered down, inducing zero consumption (but the contents of the registers and SRAM are lost) This regulator is always enabled after reset.
PAGE 19
STM32F103xF, STM32F103xG Description The DMA can be used with the main peripherals: SPI, I2C, USART, general-purpose, basic and advanced-control timers TIMx, DAC, I2S, SDIO and ADC. 2.3.17 RTC (real-time clock) and backup registers The RTC and the backup registers are supplied through a switch that takes power either on VDD supply when present or through the VBAT pin. The backup registers are forty-two 16-bit registers used to store 84 bytes of user application data when VDD power is not present.
PAGE 20
Description STM32F103xF, STM32F103xG Advanced-control timers (TIM1 and TIM8) The two advanced-control timers (TIM1 and TIM8) can each be seen as a three-phase PWM multiplexed on 6 channels. They have complementary PWM outputs with programmable inserted dead-times. They can also be seen as a complete general-purpose timer.
PAGE 21
STM32F103xF, STM32F103xG Description Basic timers TIM6 and TIM7 These timers are mainly used for DAC trigger generation. They can also be used as a generic 16-bit time base. Independent watchdog The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is clocked from an independent 40 kHz internal RC and as it operates independently from the main clock, it can operate in Stop and Standby modes.
PAGE 22
Description 2.3.21 STM32F103xF, STM32F103xG Serial peripheral interface (SPI) Up to three SPIs are able to communicate up to 18 Mbits/s in slave and master modes in full-duplex and simplex communication modes. The 3-bit prescaler gives 8 master mode frequencies and the frame is configurable to 8 bits or 16 bits. The hardware CRC generation/verification supports basic SD Card/MMC modes. All SPIs can be served by the DMA controller. 2.3.
PAGE 23
STM32F103xF, STM32F103xG Description The I/Os alternate function configuration can be locked if needed following a specific sequence in order to avoid spurious writing to the I/Os registers. 2.3.27 ADC (analog to digital converter) Three 12-bit analog-to-digital converters are embedded into STM32F103xF and STM32F103xG performance line devices and each ADC shares up to 21 external channels, performing conversions in single-shot or scan modes.
PAGE 24
Description 2.3.29 STM32F103xF, STM32F103xG Temperature sensor The temperature sensor has to generate a voltage that varies linearly with temperature. The conversion range is between 2 V < VDDA < 3.6 V. The temperature sensor is internally connected to the ADC1_IN16 input channel which is used to convert the sensor output voltage into a digital value. 2.3.
PAGE 25
STM32F103xF, STM32F103xG 3 Pinouts and pin descriptions Pinouts and pin descriptions Figure 3.
PAGE 26
Pinouts and pin descriptions STM32F103xF, STM32F103xG 6$$? 633? 0% 0% 0" 0" "//4 0" 0" 0" 0" 0" 0' 6$$? 633? 0' 0' 0' 0' 0' 0' 0$ 0$ 6$$? 633? 0$ 0$ 0$ 0$ 0$ 0$ 0# 0# 0# 0! 0! Figure 4.
PAGE 27
STM32F103xF, STM32F103xG Pinouts and pin descriptions 6$$? 633? 0% 0% 0" 0" "//4 0" 0" 0" 0" 0" 0$ 0$ 0$ 0$ 0$ 0$ 0$ 0$ 0# 0# 0# 0! 0! Figure 5. STM32F103xF/G performance line LQFP100 pinout ,1&0 6$$? 633? .
PAGE 28
Pinouts and pin descriptions STM32F103xF, STM32F103xG s ͺϯ s^^ͺϯ W ϵ W ϴ KK d Ϭ W ϳ W ϲ W ϱ W ϰ W ϯ W Ϯ W ϭϮ W ϭϭ W ϭϬ W ϭϱ W ϭϰ Figure 6.
PAGE 29
STM32F103xF, STM32F103xG Pinouts and pin descriptions Table 5.
PAGE 30
Pinouts and pin descriptions STM32F103xF, STM32F103xG Table 5.
PAGE 31
STM32F103xF, STM32F103xG Pinouts and pin descriptions Table 5.
PAGE 32
Pinouts and pin descriptions STM32F103xF, STM32F103xG Table 5.
PAGE 33
STM32F103xF, STM32F103xG Pinouts and pin descriptions Table 5.
PAGE 34
Pinouts and pin descriptions STM32F103xF, STM32F103xG Table 5.
PAGE 35
STM32F103xF, STM32F103xG Pinouts and pin descriptions 4. If several peripherals share the same I/O pin, to avoid conflict between these alternate functions only one peripheral should be enabled at a time through the peripheral clock enable bit (in the corresponding RCC peripheral clock enable register). 5. PC13, PC14 and PC15 are supplied through the power switch.
PAGE 36
Pinouts and pin descriptions STM32F103xF, STM32F103xG Table 6. FSMC pin definition FSMC Pins 36/136 Downloaded from Arrow.com.
PAGE 37
STM32F103xF, STM32F103xG Pinouts and pin descriptions Table 6.
PAGE 38
Memory mapping 4 STM32F103xF, STM32F103xG Memory mapping The memory map is shown in Figure 7. 38/136 Downloaded from Arrow.com.
PAGE 39
STM32F103xF, STM32F103xG Memory mapping Figure 7. Memory map X&&&& &&&& X% X$&&& &&&& -BYTE BLOCK #ORTEX - gS INTERNAL PERIPHERALS -BYTE BLOCK .
PAGE 40
Electrical characteristics STM32F103xF, STM32F103xG 5 Electrical characteristics 5.1 Parameter conditions Unless otherwise specified, all voltages are referenced to VSS. 5.1.1 Minimum and maximum values Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at TA = 25 °C and TA = TAmax (given by the selected temperature range).
PAGE 41
STM32F103xF, STM32F103xG 5.1.6 Electrical characteristics Power supply scheme Figure 10. Power supply scheme 9%$7 9 %DFNXS FLUFXLWU\ 26& . 57& :DNH XS ORJLF %DFNXS UHJLVWHUV 287 *3 , 2V ,1 /HYHO VKLIWHU 3R ZHU VZL WFK ,2 /RJLF .HUQHO ORJLF &38 'LJLWDO 0HPRULHV 9'' 9'' 5HJXODWRU î Q) î ) 966 9'' 9''$ 95() Q) ) Q) ) 95() 95() $'& '$& $QDORJ 5&V 3// 966$ DL Caution: In Figure 10, the 4.
PAGE 42
Electrical characteristics 5.1.7 STM32F103xF, STM32F103xG Current consumption measurement Figure 11. Current consumption measurement scheme )$$?6"!4 6"!4 )$$ 6$$ 6$$! AI 42/136 Downloaded from Arrow.com.
PAGE 43
STM32F103xF, STM32F103xG 5.2 Electrical characteristics Absolute maximum ratings Stresses above the absolute maximum ratings listed in Table 7: Voltage characteristics, Table 8: Current characteristics, and Table 9: Thermal characteristics may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Table 7.
PAGE 44
Electrical characteristics STM32F103xF, STM32F103xG Table 9. Thermal characteristics Symbol TSTG TJ Ratings Storage temperature range Maximum junction temperature 5.3 Operating conditions 5.3.1 General operating conditions Value Unit –65 to +150 °C 150 °C Table 10.
PAGE 45
STM32F103xF, STM32F103xG 5.3.2 Electrical characteristics Operating conditions at power-up / power-down The parameters given in Table 11 are derived from tests performed under the ambient temperature condition summarized in Table 10. Table 11. Operating conditions at power-up / power-down Symbol Parameter VDD rise time rate tVDD 5.3.
PAGE 46
Electrical characteristics 5.3.4 STM32F103xF, STM32F103xG Embedded reference voltage The parameters given in Table 13 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 10. Table 13. Embedded internal reference voltage Symbol Conditions Min Typ –40 °C < TA < +105 °C 1.16 1.20 1.26 V –40 °C < TA < +85 °C 1.16 1.20 1.24 V ADC sampling time when TS_vrefint(1) reading the internal reference voltage - - 5.1 17.
PAGE 47
STM32F103xF, STM32F103xG Electrical characteristics Table 14. Maximum current consumption in Run mode, code with data processing running from Flash Symbol Parameter Conditions External clock(2), all peripherals enabled IDD Supply current in Run mode fHCLK Max(1) TA = 85 °C TA = 105 °C 72 MHz 68 69 48 MHz 51 51 36 MHz 41 41 24 MHz 29 30 16 MHz 22 22.5 8 MHz 12.5 14 72 MHz 39 39 48 MHz 29.5 30 24 24.5 17.5 19 16 MHz 14 15 8 MHz 8.5 10.
PAGE 48
Electrical characteristics STM32F103xF, STM32F103xG Figure 12. Typical current consumption in Run mode versus frequency (at 3.6 V) code with data processing running from RAM, peripherals enabled #ONSUMPTION M! -(Z -(Z -(Z -(Z -(Z -(Z 4EMPERATURE # AI Figure 13. Typical current consumption in Run mode versus frequency (at 3.
PAGE 49
STM32F103xF, STM32F103xG Electrical characteristics Table 16. Maximum current consumption in Sleep mode, code running from Flash or RAM Max(1) Symbol Parameter Conditions External clock(2), all peripherals enabled IDD Supply current in Sleep mode External clock(2), all peripherals disabled fHCLK Unit TA = 85 °C TA = 105 °C 72 MHz 47.5 48.5 48 MHz 34 35 36 MHz 27.5 27.5 24 MHz 20 20.5 16 MHz 15 16 8 MHz 9 11 72 MHz 9.5 11.2 48 MHz 7.7 9.5 36 MHz 6.9 8.5 24 MHz 5.9 7.
PAGE 50
Electrical characteristics STM32F103xF, STM32F103xG Table 17. Typical and maximum current consumptions in Stop and Standby modes Typ(1) Symbol Parameter Conditions Max VDD/VBA VDD/VBA VDD/VBA TA = TA = T = 2.0 V T = 2.4 V T = 3.
PAGE 51
STM32F103xF, STM32F103xG Electrical characteristics Figure 15. Typical current consumption in Stop mode with regulator in run mode versus temperature at different VDD values #ONSUMPTION ȝ! 6 6 6 6 6 # # # # 4EMPERATURE # AI DocID16554 Rev 4 51/136 132 Downloaded from Arrow.com.
PAGE 52
Electrical characteristics STM32F103xF, STM32F103xG Figure 16. Typical current consumption in Stop mode with regulator in low-power mode versus temperature at different VDD values #ONSUMPTION ȝ! 6 6 6 6 6 # # # # 4EMPERATURE # AI Figure 17.
PAGE 53
STM32F103xF, STM32F103xG Electrical characteristics Typical current consumption The MCU is placed under the following conditions: • All I/O pins are in input mode with a static value at VDD or VSS (no load). • All peripherals are disabled except if it is explicitly mentioned. • The Flash access time is adjusted to fHCLK frequency (0 wait state from 0 to 24 MHz, 1 wait state from 24 to 48 MHZ and 2 wait states above). • Ambient temperature and VDD supply voltage conditions summarized in Table 10.
PAGE 54
Electrical characteristics STM32F103xF, STM32F103xG Table 19. Typical current consumption in Sleep mode, code running from Flash or RAM Typ(1) Symbol Parameter Conditions (3) External clock IDD Supply current in Sleep mode fHCLK All peripherals All peripherals enabled(2) disabled 72 MHz 32.5 7 48 MHz 23 5 36 MHz 17.7 4 24 MHz 12.2 3.1 16 MHz 8.4 2.3 8 MHz 4.6 1.5 4 MHz 3 1.3 2 MHz 2.15 1.25 1 MHz 1.7 1.2 500 kHz 1.5 1.15 125 kHz 1.35 1.15 64 MHz 28.7 5.
PAGE 55
STM32F103xF, STM32F103xG Electrical characteristics On-chip peripheral current consumption The current consumption of the on-chip peripherals is given in Table 20.
PAGE 56
Electrical characteristics STM32F103xF, STM32F103xG Table 20. Peripheral current consumption(1) (continued) Peripheral Current consumption APB1-Bridge 8,61 TIM2 37,22 TIM3 36,39 TIM4 35,56 TIM5 33,61 TIM6 7,78 TIM7 7,78 TIM12 19,17 TIM13 12,22 TIM14 13,33 (3) 8,33 (3) SPI3/I2S3 8,33 USART2 12,22 USART3 12,22 UART4 12,22 UART5 12,22 I2C1 10,28 I2C2 10,28 USB 18,89 CAN1 18,89 SPI2/I2S2 APB1 (up to 36 MHz) 56/136 Downloaded from Arrow.com.
PAGE 57
STM32F103xF, STM32F103xG Electrical characteristics Table 20. Peripheral current consumption(1) (continued) Peripheral APB2 (up to 72 MHz) Current consumption APB2-Bridge 2,78 GPIOA 7,64 GPIOB 7,64 GPIOC 7,64 GPIOD 8,47 GPIOE 8,47 GPIOF 8,19 GPIOG 8,19 SPI1 5,14 USART1 16,67 TIM1 28,47 TIM8 24,31 TIM9 11,81 TIM10 8,47 TIM11 8,47 (5)(6) 17,68 (5)(6) ADC2 15,54 ADC3(5)(6) 16,43 ADC1 1.
PAGE 58
Electrical characteristics STM32F103xF, STM32F103xG Table 21. High-speed external user clock characteristics Symbol Parameter Conditions fHSE_ext User external clock source frequency(1) VHSEH OSC_IN input pin high level voltage VHSEL OSC_IN input pin low level voltage tw(HSE) tw(HSE) OSC_IN high or low time(1) tr(HSE) tf(HSE) Cin(HSE) Typ Max Unit 1 8 25 MHz 0.7VDD - VDD VSS - 0.
PAGE 59
STM32F103xF, STM32F103xG Electrical characteristics Figure 18. High-speed external clock source AC timing diagram 6(3%( 6(3%, TR (3% TF (3% T7 (3% /3#?). ), T7 (3% T 4(3% %XTERNAL CLOCK SOURCE F(3%?EXT 34- & AI Figure 19. Low-speed external clock source AC timing diagram 9/6(+ 9/6(/ WU /6( WI /6( W: /6( W: /6( W 7/6( ([WHUQDO FORFN VRXUFH I/6(BH[W 26& B,1 ,/ 670 ) DL DocID16554 Rev 4 59/136 132 Downloaded from Arrow.com.
PAGE 60
Electrical characteristics STM32F103xF, STM32F103xG High-speed external clock generated from a crystal/ceramic resonator The high-speed external (HSE) clock can be supplied with a 4 to 16 MHz crystal/ceramic resonator oscillator. All the information given in this paragraph are based on characterization results obtained with typical external components specified in Table 23.
PAGE 61
STM32F103xF, STM32F103xG Electrical characteristics Figure 20. Typical application with an 8 MHz crystal 5HVRQDWRU ZLWK LQWHJUDWHG FDSDFLWRUV &/ 0+] UHVRQDWRU &/ I+6( 26&B,1 5(;7 5) 26&B28 7 %LDV FRQWUROOHG JDLQ 670 ) DL 1. REXT value depends on the crystal characteristics. DocID16554 Rev 4 61/136 132 Downloaded from Arrow.com.
PAGE 62
Electrical characteristics STM32F103xF, STM32F103xG Low-speed external clock generated from a crystal/ceramic resonator The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal/ceramic resonator oscillator. All the information given in this paragraph are based on characterization results obtained with typical external components specified in Table 24.
PAGE 63
STM32F103xF, STM32F103xG Electrical characteristics Figure 21. Typical application with a 32.768 kHz crystal 5HVRQDWRU ZLWK LQWHJUDWHG FDSDFLWRUV &/ I/6( 26& B,1 %LDV 5) FRQWUROOHG JDLQ N+ ] UHVRQDWRU 26& B28 7 &/ 670 ) DL 5.3.7 Internal clock source characteristics The parameters given in Table 25 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 10. High-speed internal (HSI) RC oscillator Table 25.
PAGE 64
Electrical characteristics STM32F103xF, STM32F103xG Low-speed internal (LSI) RC oscillator Table 26. LSI oscillator characteristics (1) Symbol fLSI(2) tsu(LSI) (3) IDD(LSI)(3) Parameter Min Typ Max Unit 30 40 60 kHz LSI oscillator startup time - - 85 µs LSI oscillator power consumption - 0.65 1.2 µA Frequency 1. VDD = 3 V, TA = –40 to 105 °C unless otherwise specified. 2. Guaranteed by characterization results, not tested in production. 3.
PAGE 65
STM32F103xF, STM32F103xG 5.3.8 Electrical characteristics PLL characteristics The parameters given in Table 28 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 10. Table 28. PLL characteristics Value Symbol Parameter Unit Min Typ Max(1) PLL input clock(2) 1 8.
PAGE 66
Electrical characteristics STM32F103xF, STM32F103xG Table 30. Flash memory endurance and data retention Value Symbol NEND tRET Parameter Endurance Data retention Conditions TA = –40 to +85 °C (6 suffix versions) TA = –40 to +105 °C (7 suffix versions) 10 1 kcycle(2) at TA = 85 °C 30 1 kcycle (2) 10 kcycles at TA = 105 °C 10 (2) 20 at TA = 55 °C 1. Guaranteed by characterization results, not tested in production. 2. Cycling performed over the whole temperature range.
PAGE 67
STM32F103xF, STM32F103xG 5.3.10 Electrical characteristics FSMC characteristics Asynchronous waveforms and timings Figure 22 through Figure 25 represent asynchronous waveforms and Table 31 through Table 35 provide the corresponding timings. The results shown in these tables are obtained with the following FSMC configuration: Note: • AddressSetupTime = 0 • AddressHoldTime = 1 • DataSetupTime = 1 On all tables, the tHCLK is the HCLK clock period. Figure 22.
PAGE 68
Electrical characteristics STM32F103xF, STM32F103xG Table 31. Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings(1) Symbol Parameter Min Max Unit 5tHCLK + 0.5 5tHCLK + 2 ns 0.5 1.
PAGE 69
STM32F103xF, STM32F103xG Electrical characteristics Table 32. Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings(1) Symbol Parameter Min Max Unit tw(NE) FSMC_NE low time 3tHCLK + 0.5 3tHCLK + 1.5 ns tv(NWE_NE) FSMC_NEx low to FSMC_NWE low tHCLK + 0.5 tHCLK + 1.5 ns tw(NWE) FSMC_NWE low time tHCLK – 0.5 tHCLK + 1 ns th(NE_NWE) FSMC_NWE high to FSMC_NE high hold time tHCLK – 0.
PAGE 70
Electrical characteristics STM32F103xF, STM32F103xG Figure 24. Asynchronous multiplexed PSRAM/NOR read waveforms TW .% &3-#?.% TV ./%?.% T H .%?./% &3-#?./% T W ./% &3-#?.7% TV !?.% &3-#?!; = T H !?./% !DDRESS TV ",?.% TH ",?./% &3-#?.",; = .", TH $ATA?.% TSU $ATA?.% T V !?.% TSU $ATA?./% !DDRESS &3-#? !$; = T V .!$6?.% TH $ATA?./% $ATA TH !$?.!$6 TW .!$6 &3-#?.!$6 AI B Table 34. Asynchronous multiplexed PSRAM/NOR read timings(1) Symbol Parameter Downloaded from Arrow.
PAGE 71
STM32F103xF, STM32F103xG Electrical characteristics Table 34. Asynchronous multiplexed PSRAM/NOR read timings(1) (continued) Symbol Parameter Min Max Unit th(Data_NE) Data hold time after FSMC_NEx high 0 - ns th(Data_NOE) Data hold time after FSMC_NOE high 0 - ns 1. CL = 15 pF. Figure 25.
PAGE 72
Electrical characteristics STM32F103xF, STM32F103xG Table 35. Asynchronous multiplexed PSRAM/NOR write timings(1) Symbol Parameter th(A_NWE) Address hold time after FSMC_NWE high tv(BL_NE) FSMC_NEx low to FSMC_BL valid th(BL_NWE) FSMC_BL hold time after FSMC_NWE high tv(Data_NADV) FSMC_NADV high to Data valid th(Data_NWE) Data hold time after FSMC_NWE high Min Max Unit 4tHCLK – 2 - ns - 0.5 ns tHCLK – 1.5 - ns - tHCLK + 6 ns tHCLK – 0.5 - ns 1. CL = 15 pF.
PAGE 73
STM32F103xF, STM32F103xG Electrical characteristics Figure 26. Synchronous multiplexed NOR/PSRAM read timings "53452. TW #,+ TW #,+ &3-#?#,+ $ATA LATENCY TD #,+, .%X, T D #,+, .%X( &3-#?.%X TD #,+, .!$6, TD #,+, .!$6( &3-#?.!$6 TD #,+, !)6 TD #,+, !6 &3-#?!; = TD #,+( ./%, TD #,+, ./%( &3-#?./% TD #,+, !$)6 TH #,+( !$6 TSU !$6 #,+( TD #,+, !$6 &3-#?!$; = !$; = TSU !$6 #,+( $ TSU .7!)46 #,+( TH #,+( !$6 $ $ TH #,+( .7!)46 &3-#?.7!)4 7!)4#&' B 7!)40/, B TSU .
PAGE 74
Electrical characteristics STM32F103xF, STM32F103xG Table 36. Synchronous multiplexed NOR/PSRAM read timings(1) Symbol Parameter Unit 27.6 - ns FSMC_CLK period td(CLKL-NExL) FSMC_CLK low to FSMC_NEx low (x = 0...2) - 0.5 ns td(CLKL-NExH) FSMC_CLK low to FSMC_NEx high (x = 0...2) 1 - ns td(CLKL-NADVL) FSMC_CLK low to FSMC_NADV low - 1 ns td(CLKL-NADVH) FSMC_CLK low to FSMC_NADV high 0.5 - ns td(CLKL-AV) FSMC_CLK low to FSMC_Ax valid (x = 16...
PAGE 75
STM32F103xF, STM32F103xG Electrical characteristics Figure 27. Synchronous multiplexed PSRAM write timings "53452. TW #,+ TW #,+ &3-#?#,+ $ATA LATENCY TD #,+, .%X, TD #,+, .%X( &3-#?.%X TD #,+, .!$6, TD #,+, .!$6( &3-#?.!$6 TD #,+, !6 TD #,+, !)6 &3-#?!; = TD #,+, .7%, TD #,+, .7%( &3-#?.7% TD #,+, !$)6 TD #,+, $ATA TD #,+, $ATA TD #,+, !$6 !$; = &3-#?!$; = $ $ &3-#?.7!)4 7!)4#&' B 7!)40/, B TSU .7!)46 #,+( TH #,+( .7!)46 TD #,+, .",( &3-#?.
PAGE 76
Electrical characteristics STM32F103xF, STM32F103xG Table 37. Synchronous multiplexed PSRAM write timings(1) Symbol Parameter Downloaded from Arrow.com. Max Unit 27.5 - ns tw(CLK) FSMC_CLK period td(CLKL-NExL) FSMC_CLK low to FSMC_Nex low (x = 0...2) - 0 ns td(CLKL-NExH) FSMC_CLK low to FSMC_NEx high (x = 0...2) 1 - ns td(CLKL-NADVL) FSMC_CLK low to FSMC_NADV low - 1 ns td(CLKL-NADVH) FSMC_CLK low to FSMC_NADV high 1 - ns td(CLKL-AV) FSMC_CLK low to FSMC_Ax valid (x = 16...
PAGE 77
STM32F103xF, STM32F103xG Electrical characteristics Figure 28. Synchronous non-multiplexed NOR/PSRAM read timings "53452. TW #,+ TW #,+ &3-#?#,+ TD #,+, .%X, TD #,+, .%X( $ATA LATENCY &3-#?.%X TD #,+, .!$6, TD #,+, .!$6( &3-#?.!$6 TD #,+, !)6 TD #,+, !6 &3-#?!; = TD #,+( ./%, TD #,+, ./%( &3-#?./% TSU $6 #,+( TH #,+( $6 TSU $6 #,+( &3-#?$; = $ TSU .7!)46 #,+( TH #,+( $6 $ $ TH #,+( .7!)46 &3-#?.7!)4 7!)4#&' B 7!)40/, B TSU .7!)46 #,+( T H #,+( .7!)46 &3-#?.
PAGE 78
Electrical characteristics STM32F103xF, STM32F103xG 1. CL = 15 pF. Figure 29. Synchronous non-multiplexed PSRAM write timings %867851 WZ &/. WZ &/. )60&B&/. 'DWD ODWHQF\ WG &/./ 1([/ W G &/./ 1([+ )60&B1([ WG &/./ 1$'9/ WG &/./ 1$'9+ )60&B1$'9 WG &/./ $,9 WG &/./ $9 )60&B$> @ WG &/./ 12(+ WG &/.+ 12(/ )60&B12( WG &/./ $',9 WG &/./ $'9 )60&B$'> @ WK &/.+ $'9 WVX $'9 &/.+ WVX $'9 &/.+ $'> @ ' WVX 1:$,79 &/.+ WK &/.+ $'9 ' WK &/.
PAGE 79
STM32F103xF, STM32F103xG Electrical characteristics 1. CL = 15 pF. PC Card/CompactFlash controller waveforms and timings Figure 30 through Figure 35 represent synchronous waveforms and Table 42 provides the corresponding timings. The results shown in this table are obtained with the following FSMC configuration: • COM.FSMC_SetupTime = 0x04; • COM.FSMC_WaitSetupTime = 0x07; • COM.FSMC_HoldSetupTime = 0x04; • COM.FSMC_HiZSetupTime = 0x00; • ATT.FSMC_SetupTime = 0x04; • ATT.
PAGE 80
Electrical characteristics STM32F103xF, STM32F103xG Figure 31. PC Card/CompactFlash controller waveforms for common memory write access )60&B1&( B )60&B1&( B +LJK WY 1&( B $ WK 1&( B $, )60&B$> @ WK 1&( B 15(* WK 1&( B 1,25' WK 1&( B 1,2:5 WG 15(* 1&( B WG 1,25' 1&( B )60&B15(* )60&B1,2:5 )60&B1,25' WG 1&( B 1:( WZ 1:( WG 1:( 1&( B )60&B1:( )60&B12( 0(0[+,= WG ' 1:( WY 1:( ' WK 1:( ' )60&B'> @ DL E 80/136 Downloaded from Arrow.com.
PAGE 81
STM32F103xF, STM32F103xG Electrical characteristics Figure 32. PC Card/CompactFlash controller waveforms for attribute memory read access )60&B1&( B WY 1&( B $ WK 1&( B $, )60&B1&( B +LJK )60&B$> @ )60&B1,2:5 )60&B1,25' WG 15(* 1&( B WK 1&( B 15(* )60&B15(* )60&B1:( WG 1&( B 12( WZ 12( WG 12( 1&( B )60&B12( WVX ' 12( WK 12( ' )60&B'> @ DL E 1. Only data bits 0...7 are read (bits 8...15 are disregarded). DocID16554 Rev 4 81/136 132 Downloaded from Arrow.com.
PAGE 82
Electrical characteristics STM32F103xF, STM32F103xG Figure 33. PC Card/CompactFlash controller waveforms for attribute memory write access )60&B1&( B )60&B1&( B +LJK WY 1&( B $ WK 1&( B $, )60&B$> @ )60&B1,2:5 )60&B1,25' WG 15(* 1&( B WK 1&( B 15(* )60&B15(* WG 1&( B 1:( WZ 1:( )60&B1:( WG 1:( 1&( B )60&B12( WY 1:( ' )60&B'> @ DL E 1. Only data bits 0...7 are driven (bits 8...15 remains HiZ). Figure 34.
PAGE 83
STM32F103xF, STM32F103xG Electrical characteristics Figure 35. PC Card/CompactFlash controller waveforms for I/O space write access )60&B1&( B )60&B1&( B WY 1&([ $ WK 1&( B $, )60&B$> @ )60&B15(* )60&B1:( )60&B12( )60&B1,25' WG 1&( B 1,2:5 WZ 1,2:5 )60&B1,2:5 $77[+,= WY 1,2:5 ' WK 1,2:5 ' )60&B'> @ DL F Table 40.
PAGE 84
Electrical characteristics STM32F103xF, STM32F103xG Table 41. Switching characteristics for PC Card/CF read and write cycles in I/O space Symbol Parameter tw(NIOWR) FSMC_NIOWR low width tv(NIOWR-D) FSMC_NIOWR low to FSMC_D[15:0] valid th(NIOWR-D) FSMC_NIOWR high to FSMC_D[15:0] invalid Min Max Unit 8 THCLK - ns - 5 THCLK 4 ns 11THCLK 7 - ns td(NCE4_1-NIOWR) FSMC_NCE4_1 low to FSMC_NIOWR valid - 5THCLK + 1 ns th(NCEx-NIOWR) FSMC_NCEx high to FSMC_NIOWR invalid 5THCLK 2.
PAGE 85
STM32F103xF, STM32F103xG Electrical characteristics Figure 36. NAND controller waveforms for read access )60&B1&([ /RZ $/( )60&B$ &/( )60&B$ )60&B1:( WK 12( $/( WG $/( 12( )60&B12( 15( WVX ' 12( WK 12( ' )60&B'> @ DL E Figure 37. NAND controller waveforms for write access )60&B1&([ $/( )60&B$ &/( )60&B$ WG $/( 1:( WK 1:( $/( )60&B1:( )60&B12( 15( WY 1:( ' WK 1:( ' )60&B'> @ AI C DocID16554 Rev 4 85/136 132 Downloaded from Arrow.com.
PAGE 86
Electrical characteristics STM32F103xF, STM32F103xG Figure 38. NAND controller waveforms for common memory read access )60&B1&([ /RZ $/( )60&B$ &/( )60&B$ WG $/( 12( WK 12( $/( )60&B1:( WZ 12( )60&B12( WVX ' 12( WK 12( ' )60&B'> @ DL E Figure 39. NAND controller waveforms for common memory write access )60&B1&([ /RZ $/( )60&B$ &/( )60&B$ WG $/( 1:( WZ 1:( WK 1:( $/( )60&B1:( )60&B12( WG ' 1:( WY 1:( ' WK 1:( ' )60&B'> @ DL E Table 42.
PAGE 87
STM32F103xF, STM32F103xG Electrical characteristics Table 43. Switching characteristics for NAND Flash write cycles(1) Symbol Parameter Min Max Unit 3tHCLK 3tHCLK ns - 0 ns tw(NWE) FSMC_NWE low width tv(NWE-D) FSMC_NWE low to FSMC_D[15:0] valid th(NWE-D) FSMC_NWE high to FSMC_D[15:0] invalid 2tHCLK + 2 - ns td(ALE-NWE) FSMC_ALE valid before FSMC_NWE low - 3tHCLK + 1.
PAGE 88
Electrical characteristics 5.3.11 STM32F103xF, STM32F103xG EMC characteristics Susceptibility tests are performed on a sample basis during device characterization. Functional EMS (electromagnetic susceptibility) While a simple application is executed on the device (toggling 2 LEDs through I/O ports). the device is stressed by two electromagnetic events until a failure occurs.
PAGE 89
STM32F103xF, STM32F103xG Electrical characteristics To complete these trials, ESD stress can be applied directly on the device, over the range of specification values. When unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note AN1015). Electromagnetic Interference (EMI) The electromagnetic field emitted by the device are monitored while a simple application is executed (toggling 2 LEDs through the I/O ports).
PAGE 90
Electrical characteristics STM32F103xF, STM32F103xG Table 47. Electrical sensitivities Symbol LU 5.3.13 Parameter Static latch-up class Conditions Class TA = +105 °C conforming to JESD78A II level A I/O current injection characteristics As a general rule, current injection to the I/O pins, due to external voltage below VSS or above VDD (for standard, 3 V-capable I/O pins) should be avoided during normal product operation.
PAGE 91
STM32F103xF, STM32F103xG 5.3.14 Electrical characteristics I/O port characteristics General input/output characteristics Unless otherwise specified, the parameters given in Table 49 are derived from tests performed under the conditions summarized in Table 10. All I/Os are CMOS and TTL compliant. Table 49.
PAGE 92
Electrical characteristics STM32F103xF, STM32F103xG Figure 40. Standard I/O input characteristics - CMOS port 6)( 6), 6 6 $$ 6 $$ NT 6 )( /3 STAN #- 7)(MIN )NPUT RANGE NOT GUARANTEED 6 6), $$ T 6 ), 6 $$ RD REQUIREMEN #-/3 STANDA 7),MAX 6 )( UIREME DARD REQ 6$$ 6 AI B Figure 41.
PAGE 93
STM32F103xF, STM32F103xG Electrical characteristics Figure 43.
PAGE 94
Electrical characteristics STM32F103xF, STM32F103xG Table 50. Output voltage characteristics (continued) Symbol Parameter VOL(1)(4) Output low level voltage for an I/O pin when 8 pins are sunk at same time VOH(2)(4) Output high level voltage for an I/O pin when 8 pins are sourced at same time VOL(1)(4) Output low level voltage for an I/O pin when 8 pins are sunk at same time VOH(2)(4) Output high level voltage for an I/O pin when 8 pins are sourced at same time Conditions IIO = +20 mA 2.
PAGE 95
STM32F103xF, STM32F103xG Electrical characteristics Input/output AC characteristics The definition and values of input/output AC characteristics are given in Figure 44 and Table 51, respectively. Unless otherwise specified, the parameters given in Table 51 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 10. Table 51.
PAGE 96
Electrical characteristics STM32F103xF, STM32F103xG Figure 44. I/O AC characteristics definition (;7(51$/ 287387 21 &/ WU ,2 RXW WI ,2 RXW 7 0D[LPXP IUHTXHQF\ LV DFKLHYHG LI WU WI 7 DQG LI WKH GXW\ F\FOH LV ZKHQ ORDGHG E\ &/ VSHFLILHG LQ WKH WDEOH ³ , 2 $& FKDUDFWHULVWLFV´ 5.3.15 DL G NRST pin characteristics The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up resistor, RPU (see Table 49).
PAGE 97
STM32F103xF, STM32F103xG Electrical characteristics Figure 45. Recommended NRST pin protection 9'' ([WHUQDO UHVHW FLUFXLW 538 1567 ,QWHUQDO 5HVHW )LOWHU ) 670 ) DL F 1. The reset network protects the device against parasitic resets. 2. The user must ensure that the level on the NRST pin can go below the VIL(NRST) max level specified in Table 52. Otherwise the reset will not be taken into account by the device. 5.3.
PAGE 98
Electrical characteristics 5.3.17 STM32F103xF, STM32F103xG Communications interfaces I2C interface characteristics The STM32F103xF, STM32F103xD and STM32F103xGSTM32F103xF and STM32F103xG performance line I2C interface meets the requirements of the standard I2C communication protocol with the following restrictions: the I/O pins SDA and SCL are mapped to are not “true” open-drain. When configured as open-drain, the PMOS connected between the I/O pin and VDD is disabled, but is still present.
PAGE 99
STM32F103xF, STM32F103xG Electrical characteristics Figure 46. I2C bus AC waveforms and measurement circuit s ͺ/Ϯ s ͺ/Ϯ ZW ZW ^dDϯϮ Z^ ^ /ϸ ďƵƐ Z^ ^ > ^ d Z d Z W d ^ d Z d ^ d Z d ƚƐƵ;^d Ϳ ^ ƚĨ;^ Ϳ ƚƌ;^ Ϳ ƚŚ;^d Ϳ ƚƐƵ;^ Ϳ ƚŚ;^ Ϳ ƚǁ;^ >>Ϳ ƚǁ;^dK͗^d Ϳ ^ dKW ^ > ƚƌ;^ >Ϳ ƚǁ;^ >,Ϳ ƚĨ;^ >Ϳ ƚƐƵ;^dKͿ ĂŝϭϰϵϳϵĚ 1. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD. 2. Rs: Series protection resistors. 3. Rp: Pull-up resistors. 4. VDD_I2C : I2C bus supply Table 55.
PAGE 100
Electrical characteristics STM32F103xF, STM32F103xG I2S - SPI characteristics Unless otherwise specified, the parameters given in Table 56 for SPI or in Table 57 for I2S are derived from tests performed under ambient temperature, fPCLKx frequency and VDD supply voltage conditions summarized in Table 10. Refer to Section 5.3.14: I/O port characteristics for more details on the input/output alternate function characteristics (NSS, SCK, MOSI, MISO for SPI and WS, CK, SD for I2S). Table 56.
PAGE 101
STM32F103xF, STM32F103xG Electrical characteristics Figure 47. SPI timing diagram - slave mode and CPHA = 0 E^^ ŝŶƉƵƚ ƚĐ;^ <Ϳ ƚŚ;E^^Ϳ ƚ^h;E^^Ϳ ^ < /ŶƉƵƚ W, с Ϭ WK>сϬ ƚǁ;^ <,Ϳ ƚǁ;^ <>Ϳ W, с Ϭ WK>сϭ ƚǀ;^KͿ ƚĂ;^KͿ D/^K KhdW hd ƚƌ;^ <Ϳ ƚĨ;^ <Ϳ ƚŚ;^KͿ D^ K hd / dϲ Khd D ^ /E / dϭ /E ƚĚŝƐ;^KͿ >^ Khd ƚƐƵ;^/Ϳ DK^/ / EWhd >^ /E ƚŚ;^/Ϳ DL F Figure 48. SPI timing diagram - slave mode and CPHA = 1(1) 166 LQSXW 6&. ,QSXW W68 166 &3+$ &32/ &3+$ &32/ WF 6&. WZ 6&.+ WZ 6&.
PAGE 102
Electrical characteristics STM32F103xF, STM32F103xG Figure 49. SPI timing diagram - master mode(1) (IGH .33 INPUT 3#+ /UTPUT #0(! #0/, 3#+ /UTPUT TC 3#+ #0(! #0/, #0(! #0/, #0(! #0/, TSU -) -)3/ ).0 54 TW 3#+( TW 3#+, -3 "). TR 3#+ TF 3#+ ") 4 ). ,3" ). TH -) -/3) /54054 - 3" /54 TV -/ " ) 4 /54 ,3" /54 TH -/ AI 6 1. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD. 102/136 Downloaded from Arrow.com.
PAGE 103
STM32F103xF, STM32F103xG Electrical characteristics Table 57. I2S characteristics Symbol DuCy(SCK) Parameter Conditions Min Max Unit 30 70 % 1.522 1.525 Slave mode 0 6.
PAGE 104
Electrical characteristics STM32F103xF, STM32F103xG Figure 50. I2S slave timing diagram (Philips protocol)(1) &. ,QSXW WF &. &32/ &32/ WZ &.+ WK :6 WZ &./ :6 LQSXW WY 6'B67 WVX :6 6'WUDQVPLW /6% WUDQVPLW 06% WUDQVPLW %LWQ WUDQVPLW WVX 6'B65 /6% UHFHLYH 6'UHFHLYH WK 6'B67 /6% WUDQVPLW WK 6'B65 06% UHFHLYH %LWQ UHFHLYH /6% UHFHLYH DL E 1. Measurement points are done at CMOS levels: 0.3 × VDD and 0.7 × VDD. 2. LSB transmit/receive of the previously transmitted byte.
PAGE 105
STM32F103xF, STM32F103xG Electrical characteristics SD/SDIO MMC card host interface (SDIO) characteristics Unless otherwise specified, the parameters given in Table 58 are derived from tests performed under ambient temperature, fPCLKx frequency and VDD supply voltage conditions summarized in Table 10. Refer to Section 5.3.14: I/O port characteristics for more details on the input/output alternate function characteristics (D[7:0], CMD, CK). Figure 52.
PAGE 106
Electrical characteristics STM32F103xF, STM32F103xG Table 58.
PAGE 107
STM32F103xF, STM32F103xG Electrical characteristics Table 60. USB DC electrical characteristics Symbol Parameter Conditions Min.(1) Max.(1) Unit 3.0(3) 3.6 V 0.2 - Input levels VDD VDI (4) USB operating voltage(2) - Differential input sensitivity I(USB_DP, USB_DM) VCM(4) Differential common mode range Includes VDI range 0.8 2.5 VSE(4) Single ended receiver threshold 1.3 2.0 - 0.3 2.8 3.6 V Output levels VOL Static output level low RL of 1.5 kΩ to 3.
PAGE 108
Electrical characteristics 5.3.18 STM32F103xF, STM32F103xG CAN (controller area network) interface Refer to Section 5.3.14: I/O port characteristics for more details on the input/output alternate function characteristics (CAN_TX and CAN_RX). 5.3.19 12-bit ADC characteristics Unless otherwise specified, the parameters given in Table 62 are preliminary values derived from tests performed under ambient temperature, fPCLK2 frequency and VDDA supply voltage conditions summarized in Table 10.
PAGE 109
STM32F103xF, STM32F103xG Electrical characteristics 2. Guaranteed by design, not tested in production. 3. VREF+ can be internally connected to VDDA and VREF- can be internally connected to VSSA, depending on the package. Refer to Section 3: Pinouts and pin descriptions for further details. 4. For external triggers, a delay of 1/fPCLK2 must be added to the latency specified in Table 62.
PAGE 110
Electrical characteristics STM32F103xF, STM32F103xG Table 65. ADC accuracy(1) (2)(3) Symbol Parameter Test conditions ET Total unadjusted error EO Offset error EG Gain error ED Differential linearity error EL Integral linearity error fPCLK2 = 56 MHz, fADC = 14 MHz, RAIN < 10 kΩ, VDDA = 2.4 V to 3.6 V Measurements made after ADC calibration Typ Max(4) ±2 ±5 ±1.5 ±2.5 ±1.5 ±3 ±1 ±2 ±1.5 ±3 Unit LSB 1. ADC DC accuracy values are measured after internal calibration. 2.
PAGE 111
STM32F103xF, STM32F103xG Electrical characteristics Figure 56. Typical connection diagram using the ADC 670 ) 9'' 5$,1 9$,1 6DPSOH DQG KROG $'& FRQYHUWHU 97 9 5$'& $,1[ &SDUDVLWLF 97 9 ELW FRQYHUWHU & $'& ,/ $ DL 1. Refer to Table 62 for the values of RAIN, RADC and CADC. 2. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the pad capacitance (roughly 7 pF).
PAGE 112
Electrical characteristics STM32F103xF, STM32F103xG Figure 58. Power supply and reference decoupling (VREF+ connected to VDDA) 670 ) 95() 9''$ 6HH QRWH ) Q) 9 5()± 966$ 6HH QRWH DL 1. VREF+ and VREF– inputs are available only on 100-pin packages. 112/136 Downloaded from Arrow.com.
PAGE 113
STM32F103xF, STM32F103xG 5.3.20 Electrical characteristics DAC electrical specifications Table 66. DAC characteristics Symbol Parameter Min Typ Max Unit VDDA Analog supply voltage 2.4 - 3.6 V VREF+ Reference supply voltage 2.4 - 3.6 V VSSA Ground 0 - 0 V Resistive load vs. VSSA with buffer ON 5 - - kΩ Resistive load vs.
PAGE 114
Electrical characteristics STM32F103xF, STM32F103xG Table 66. DAC characteristics (continued) Symbol Min Typ Max Unit - - ±1 LSB Given for the DAC in 10-bit configuration - - ±4 LSB Given for the DAC in 12-bit configuration - - ±10 mV - - ±3 LSB Given for the DAC in 10-bit at VREF+ = 3.6 V - - ±12 LSB Given for the DAC in 12-bit at VREF+ = 3.6 V - - ±0.
PAGE 115
STM32F103xF, STM32F103xG Electrical characteristics Figure 59. 12-bit buffered /non-buffered DAC %XIIHUHG 1RQ EXIIHUHG '$& %XIIHU 5/ '$&B287[ ELW GLJLWDO WR DQDORJ FRQYHUWHU &/ AI 6 1. The DAC integrates an output buffer that can be used to reduce the output impedance and to drive external loads directly without the use of an external operational amplifier. The buffer can be bypassed by configuring the BOFFx bit in the DAC_CR register. 5.3.
PAGE 116
Package information 6 STM32F103xF, STM32F103xG Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. 116/136 Downloaded from Arrow.com.
PAGE 117
STM32F103xF, STM32F103xG 6.1 Package information LFBGA144 package information Figure 60. LFBGA144 – 144-ball low profile fine pitch ball grid array, 10 x 10 mm, 0.8 mm pitch, package outline = 6HDWLQJ SODQH GGG = $ $ $ $ $ ( H $ EDOO $ EDOO LGHQWLILHU LQGH[ DUHD ) ; ( $ ) ' ' H < 0 %27720 9,(: E EDOOV HHH 0 = < ; III 0 = 723 9,(: ; B0(B9 1. Drawing is not to scale. Table 68. LFBGA144 – 144-ball low profile fine pitch ball grid array, 10 x 10 mm, 0.
PAGE 118
Package information STM32F103xF, STM32F103xG Table 68. LFBGA144 – 144-ball low profile fine pitch ball grid array, 10 x 10 mm, 0.8 mm pitch, package mechanical data (continued) inches(1) millimeters Symbol Min Typ Max Typ Min Max eee - - 0.150 - - 0.0059 fff - - 0.080 - - 0.0031 1. Values in inches are converted from mm and rounded to 4 decimal digits. 2. STATSChipPAC package dimensions.
PAGE 119
STM32F103xF, STM32F103xG 6.2 Package information LQFP144 package information Figure 62. LQFP144 - 144-pin, 20 x 20 mm low-profile quad flat package outline 6($7,1* 3/$1( F $ $ $ & PP *$8*( 3/$1( ' / ' . $ FFF & / ' ( 3,1 ( ( E ,'(17,),&$7,21 H $B0(B9 1. Drawing is not to scale. DocID16554 Rev 4 119/136 132 Downloaded from Arrow.com.
PAGE 120
Package information STM32F103xF, STM32F103xG Table 69. LQFP144 - 144-pin, 20 x 20 mm low-profile quad flat package mechanical data inches(1) millimeters Symbol Min Typ Max Min Typ Max A - - 1.600 - - 0.0630 A1 0.050 - 0.150 0.0020 - 0.0059 A2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.170 0.220 0.270 0.0067 0.0087 0.0106 c 0.090 - 0.200 0.0035 - 0.0079 D 21.800 22.000 22.200 0.8583 0.8661 0.8740 D1 19.800 20.000 20.200 0.7795 0.7874 0.7953 D3 - 17.
PAGE 121
STM32F103xF, STM32F103xG Package information Figure 63. LQFP144 - 144-pin,20 x 20 mm low-profile quad flat package recommended footprint DL H 1. Dimensions are expressed in millimeters. DocID16554 Rev 4 121/136 132 Downloaded from Arrow.com.
PAGE 122
Package information STM32F103xF, STM32F103xG Device marking for LQFP144 package The following figure gives an example of topside marking orientation versus pin 1 identifier location. Figure 64. LQFP144 marking example (package top view) 5HYLVLRQ FRGH 3URGXFW LGHQWLILFDWLRQ 5 670 ) =)7 'DWH FRGH < :: 3LQ LGHQWLILHU 06Y 9 1.
PAGE 123
STM32F103xF, STM32F103xG 6.3 Package information LQFP100 package information Figure 65. LFP100 – 14 x 14 mm 100 pin low-profile quad flat package outline MM C ! ! ! 3%!4).' 0,!.% # '!5'% 0,!.% $ , $ ! + CCC # , $ 0). )$%.4)&)#!4)/. % % % B E ,?-%?6 1. Drawing is not to scale. Table 70. LQPF100 – 14 x 14 mm 100-pin low-profile quad flat package mechanical data Symbol inches(1) millimeters Min Typ Max Min Typ Max A - - 1.
PAGE 124
Package information STM32F103xF, STM32F103xG Table 70. LQPF100 – 14 x 14 mm 100-pin low-profile quad flat package mechanical data (continued) Symbol inches(1) millimeters Min Typ Max Min Typ Max e - 0.500 - - 0.0197 - L 0.450 0.600 0.750 0.0177 0.0236 0.0295 L1 - 1.000 - - 0.0394 - k 0° 3.5° 7° 0° 3.5° 7° ccc - - 0.08 - - 0.0031 1. Values in inches are converted from mm and rounded to 4 decimal digits. Figure 66.
PAGE 125
STM32F103xF, STM32F103xG Package information Device marking for LQFP100 package The following figure gives an example of topside marking orientation versus pin 1 identifier location. Figure 67. LQFP100 marking example (package top view) 3URGXFW LGHQWLILFDWLRQ 670 ) 9*7 5 5HYLVLRQ FRGH 'DWH FRGH < :: 3LQ LQGHQWLILHU 06Y 9 1.
PAGE 126
Package information 6.4 STM32F103xF, STM32F103xG LQFP64 package information Figure 68. LFP64 – 10 x 10 mm 64 pin low-profile quad flat package outline PP *$8*( 3/$1( F $ $ $ 6($7,1* 3/$1( & $ FFF & ' ' ' . / / ( ( ( E 3,1 ,'(17,),&$7,21 H :B0(B9 1. Drawing is not in scale. Table 71. LQFP64 – 10 x 10 mm 64 pin low-profile quad flat package mechanical data inches(1) millimeters Symbol Min Typ Max Min Typ Max A - - 1.600 - - 0.
PAGE 127
STM32F103xF, STM32F103xG Package information Table 71. LQFP64 – 10 x 10 mm 64 pin low-profile quad flat package mechanical data (continued) inches(1) millimeters Symbol Min Typ Max Min Typ Max E3 - 7.500 - - 0.2953 - e - 0.500 - - 0.0197 - θ 0° 3.5° 7° 0° 3.5° 7° L 0.450 0.600 0.750 0.0177 0.0236 0.0295 L1 - 1.000 - - 0.0394 - ccc - - 0.080 - - 0.0031 1. Values in inches are converted from mm and rounded to 4 decimal digits. Figure 69.
PAGE 128
Package information STM32F103xF, STM32F103xG Device marking for LQFP64 package The following figure gives an example of topside marking orientation versus pin 1 identifier location. Figure 70. LQFP64 marking example (package top view) 5HYLVLRQ FRGH 5 3URGXFW LGHQWLILFDWLRQ 670 ) 5)7 'DWH FRGH < :: 3LQ LGHQWLILHU 06Y 9 1.
PAGE 129
STM32F103xF, STM32F103xG 6.5 Package information Thermal characteristics The maximum chip junction temperature (TJmax) must never exceed the values given in Table 10: General operating conditions on page 44.
PAGE 130
Package information 6.5.2 STM32F103xF, STM32F103xG Selecting the product temperature range When ordering the microcontroller, the temperature range is specified in the ordering information scheme shown in Table 73: STM32F103xF and STM32F103xG ordering information scheme. Each temperature range suffix corresponds to a specific guaranteed ambient temperature at maximum dissipation and, to a specific maximum junction temperature.
PAGE 131
STM32F103xF, STM32F103xG Package information Using the values obtained in Table 72 TJmax is calculated as follows: – For LQFP100, 46 °C/W TJmax = 115 °C + (46 °C/W × 134 mW) = 115 °C + 6.2 °C = 121.2 °C This is within the range of the suffix 7 version parts (–40 < TJ < 125 °C). In this case, parts must be ordered at least with the temperature range suffix 7 (see Section 7: Part numbering). Figure 71. LQFP100 PD max vs.
PAGE 132
Part numbering 7 STM32F103xF, STM32F103xG Part numbering Table 73. STM32F103xF and STM32F103xG ordering information scheme Example: STM32 F 103 R F T 6 xxx Device family STM32 = ARM-based 32-bit microcontroller Product type F = general-purpose Device subfamily 103 = performance line Pin count R = 64 pins V = 100 pins Z = 144 pins Flash memory size F = 768 Kbytes of Flash memory G = 1 Mbyte of Flash memory Package H = BGA T = LQFP Temperature range 6 = Industrial temperature range, –40 to 85 °C.
PAGE 133
STM32F103xF, STM32F103xG 8 Revision history Revision history Table 74. Document revision history Date Revision 27-Oct-2009 1 Initial release. 2 LQFP64 package mechanical data updated: see Figure 66: LQFP64 – 10 x 10 mm 64 pin low-profile quad flat package outline and Table 71: LQFP64 – 10 x 10 mm 64 pin low-profile quad flat package mechanical data. Internal code removed from Table 73: STM32F103xF and STM32F103xG ordering information scheme.
PAGE 134
Revision history STM32F103xF, STM32F103xG Table 74. Document revision history Date 18-Jan-2012 134/136 Downloaded from Arrow.com.
PAGE 135
STM32F103xF, STM32F103xG Table 74. Revision history Document revision history Date 15-May-2015 Revision Changes 4 Added document status on first page. Replace DAC1_OUT/DAC2_OUT by DAC_OUT1/DAC_OUT2, and updated TIM5 in Figure 1: STM32F103xF and STM32F103xG performance line block diagram on page 12. Replaced USBDP/USBDM by USB_DP/USB_DM in the whole document. Updated notes related to electrical values guaranteed by characterization results. Updated Table 20: Peripheral current consumption.
PAGE 136
STM32F103xF, STM32F103xG IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement.