Datasheet

Electrical characteristics STM32F103xC, STM32F103xD, STM32F103xE
96/143 DS5792 Rev 13
5.3.17 Communications interfaces
I
2
C interface characteristics
The STM32F103xC, STM32F103xD and STM32F103xESTM32F103xF and STM32F103xG
performance line
I
2
C interface meets the requirements of the standard I
2
C communication
protocol with the following restrictions: the I/O pins SDA and SCL are mapped to are not
“true” open-drain. When configured as open-drain, the PMOS connected between the I/O
pin and V
DD
is disabled, but is still present.
The I
2
C characteristics are described in Table 51. Refer also to Section 5.3.14: I/O port
characteristics
for more details on the input/output alternate function characteristics (SDA
and SCL)
.
Table 51. I
2
C characteristics
Symbol Parameter
Standard mode
I
2
C
(1)(2)
1.
Guaranteed by design.
Fast mode I
2
C
(1)(2)
2. f
PCLK1
must be at least 2 MHz to achieve standard mode I
2
C frequencies. It must be at least 4 MHz to
achieve the fast mode I
2
C frequencies and it must be a multiple of 10 MHz in order to reach the I2C fast
mode maximum clock speed of 400 kHz.
Unit
Min Max Min Max
t
w(SCLL)
SCL clock low time 4.7 - 1.3 -
µs
t
w(SCLH)
SCL clock high time 4.0 - 0.6 -
t
su(SDA)
SDA setup time 250 - 100 -
ns
t
h(SDA)
SDA data hold time - 3450
(3)
-900
(3)
3. The device must internally provide a hold time of at least 300ns for the SDA signal in order to bridge the
undefined region on the falling edge of SCL.
t
r(SDA)
t
r(SCL)
SDA and SCL rise time - 1000 - 300
t
f(SDA)
t
f(SCL)
SDA and SCL fall time - 300 - 300
t
h(STA)
Start condition hold time 4.0 - 0.6 -
µs
t
su(STA)
Repeated Start condition
setup time
4.7 - 0.6 -
t
su(STO)
Stop condition setup time 4.0 - 0.6 - μs
t
w(STO:STA)
Stop to Start condition time
(bus free)
4.7 - 1.3 - μs
C
b
Capacitive load for each bus
line
- 400 - 400 pF
t
SP
Pulse width of the spikes
that are suppressed by the
analog filter for standard and
fast mode
050
(4)
4. The minimum width of the spikes filtered by the analog filter is above t
SP
(max).
050
(4)
μs