Datasheet

DS5792 Rev 13 83/143
STM32F103xC, STM32F103xD, STM32F103xE Electrical characteristics
135
NAND controller waveforms and timings
Figure 38 through Figure 41 represent synchronous waveforms and Table 39 provides the
corresponding timings. The results shown in this table are obtained with the following FSMC
configuration:
COM.FSMC_SetupTime = 0x01;
COM.FSMC_WaitSetupTime = 0x03;
COM.FSMC_HoldSetupTime = 0x02;
COM.FSMC_HiZSetupTime = 0x01;
ATT.FSMC_SetupTime = 0x01;
ATT.FSMC_WaitSetupTime = 0x03;
ATT.FSMC_HoldSetupTime = 0x02;
ATT.FSMC_HiZSetupTime = 0x01;
Bank = FSMC_Bank_NAND;
MemoryDataWidth = FSMC_MemoryDataWidth_16b;
ECC = FSMC_ECC_Enable;
ECCPageSize = FSMC_ECCPageSize_512Bytes;
TCLRSetupTime = 0;
TARSetupTime = 0;
Figure 38. NAND controller waveforms for read access
)60&B1:(
)60&B12(15(
)60&B'>@
W
VX'12(
W
K12('
DLE
$/()60&B$
&/()60&B$
)60&B1&([
/RZ
W
G$/(12(
W
K12($/(