Datasheet
Pinouts and pin descriptions STM32F103xC, STM32F103xD, STM32F103xE
36/143 DS5792 Rev 13
C8 - - - - 126 PG11 I/O FT PG11 FSMC_NCE4_2 -
B8 - - - - 127 PG12 I/O FT PG12 FSMC_NE4 -
D7 - - - - 128 PG13 I/O FT PG13 FSMC_A24 -
C7 - - - - 129 PG14 I/O FT PG14 FSMC_A25 -
E6 - - - - 130 V
SS_11
S- V
SS_11
--
F6 - - - - 131 V
DD_11
S- V
DD_11
--
B7 - - - - 132 PG15 I/O FT PG15 - -
A7 A7 A4 55 89 133 PB3 I/O FT JTDO SPI3_SCK / I2S3_CK/
PB3
/
TRACES
WO
TIM2_CH2 /
SPI1_SCK
A6 A6 B4 56 90 134 PB4 I/O FT NJTRST SPI3_MISO
PB4
/
TIM3_CH1
SPI1_MISO
B6 C5 A5 57 91 135 PB5 I/O - PB5
I2C1_SMBA/ SPI3_MOSI
I2S3_SD
TIM3_CH2 /
SPI1_MOSI
C6 B5 B5 58 92 136 PB6 I/O FT PB6 I2C1_SCL
(9)
/ TIM4_CH1
(9)
USART1_TX
D6 A5 C5 59 93 137 PB7 I/O FT PB7
I2C1_SDA
(9)
/ FSMC_NADV
/ TIM4_CH2
(9)
USART1_RX
D5 D5 A6 60 94 138 BOOT0 I - BOOT0 - -
C5 B4 D5 61 95 139 PB8 I/O FT PB8 TIM4_CH3
(9)
/SDIO_D4
I2C1_SCL/
CAN_RX
B5 A4 B6 62 96 140 PB9 I/O FT PB9 TIM4_CH4
(9)
/SDIO_D5
I2C1_SDA /
CAN_TX
A5 D4 - - 97 141 PE0 I/O FT PE0 TIM4_ETR / FSMC_NBL0 -
A4 C4 - - 98 142 PE1 I/O FT PE1 FSMC_NBL1 -
E5 E5 A7 63 99 143 V
SS_3
S- V
SS_3
--
F5 F5 A8 64
10
0
144 V
DD_3
S- V
DD_3
--
1. I = input, O = output, S = supply.
2. FT = 5 V tolerant.
3. Function availability depends on the chosen device.
4. If several peripherals share the same I/O pin, to avoid conflict between these alternate functions only one peripheral should
be enabled at a time through the peripheral clock enable bit (in the corresponding RCC peripheral clock enable register).
Table 5. High-density STM32F103xC/D/E pin definitions (continued)
Pins
Pin name
Type
(1)
I / O Level
(2)
Main
function
(3)
(after reset)
Alternate functions
(4)
LFBGA144
LFBGA100
WLCSP64
LQFP64
LQFP100
LQFP144
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