Datasheet

ManualsBrandsST ManualsEmbedded Processors & ControllersMicrocontroller 32bit 512KB LQFP

July 2018 DS5792 Rev 13 1/143

STM32F103xC, STM32F103xD,

STM32F103xE

High-density performance line Arm

-based 32-bit MCU with 256 to 512KB

Flash, USB, CAN, 11 timers, 3 ADCs, 13 communication interfaces

Datasheet − production data

Features

• Core: Arm

32-bit Cortex

-M3 CPU

– 72 MHz maximum frequency, 1.25 DMIPS/MHz

(Dhrystone 2.1) performance at 0 wait state

memory access

– Single-cycle multiplication and hardware

division

• Memories

– 256 to 512 Kbytes of Flash memory

– up to 64 Kbytes of SRAM

– Flexible static memory controller with 4 Chip

Select. Supports Compact Flash,

SRAM,

PSRAM, NOR and NAND

memories

– LCD parallel interface, 8080/6800 modes

• Clock, reset and supply management

– 2.0 to 3.6 V application supply and I/Os

– POR, PDR, and programmable voltage detector

(PVD)

– 4-to-16 MHz crystal oscillator

– Internal 8 MHz factory-trimmed RC

– Internal 40 kHz RC with calibration

– 32 kHz oscillator for RTC with calibration

• Low power

– Sleep, Stop and Standby modes

–V

BAT

supply for RTC and backup registers

• 3 × 12-bit, 1 µs A/D converters (up to 21

channels)

– Conversion range: 0 to 3.6 V

– Triple-sample and hold capability

– Temperature sensor

• 2 × 12-bit D/A converters

• DMA: 12-channel DMA controller

– Supported peripherals: timers, ADCs, DAC,

SDIO, I

Ss, SPIs, I

Cs and USARTs

• Debug mode

– Serial wire debug (SWD) & JTAG interfaces

–Cortex

-M3 Embedded Trace Macrocell™

• Up to 112 fast I/O ports

– 51/80/112 I/Os, all mappable on 16 external

interrupt vectors and almost all 5 V-tolerant

• Up to 11 timers

– Up to four 16-bit timers, each with up to 4

IC/OC/PWM or pulse counter and quadrature

(incremental) encoder input

– 2 × 16-bit motor control PWM timers with dead-

time generation and emergency stop

– 2 × watchdog timers (Independent and Window)

– SysTick timer: a 24-bit downcounter

– 2 × 16-bit basic timers to drive the DAC

• Up to 13 communication interfaces

– Up to 2 × I

C interfaces (SMBus/PMBus)

– Up to 5 USARTs (ISO 7816 interface, LIN, IrDA

capability, modem control)

– Up to 3 SPIs (18 Mbit/s), 2 with I

S interface

multiplexed

– CAN interface (2.0B Active)

– USB 2.0 full speed interface

– SDIO interface

• CRC calculation unit, 96-bit unique ID

• ECOPACK

packages

Table 1.Device summary

Reference Part number

STM32F103xC

STM32F103RC STM32F103VC

STM32F103ZC

STM32F103xD

STM32F103RD STM32F103VD

STM32F103ZD

STM32F103xE

STM32F103RE STM32F103ZE

STM32F103VE

LQFP64 10 × 10 mm,

LQFP100 14 × 14 mm,

LQFP144 20 × 20 mm

LFBGA100 10 × 10 mm

LFBGA144 10 × 10 mm

WLCSP64

www.st.com

Summary of content (143 pages)

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STM32F103xC, STM32F103xD, STM32F103xE High-density performance line Arm®-based 32-bit MCU with 256 to 512KB Flash, USB, CAN, 11 timers, 3 ADCs, 13 communication interfaces Datasheet −production data Features • Core: Arm® 32-bit Cortex®-M3 CPU – – WLCSP64 72 MHz maximum frequency, 1.25 DMIPS/MHz (Dhrystone 2.
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Contents STM32F103xC, STM32F103xD, STM32F103xE Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2/143 2.1 Device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.2 Full compatibility throughout the family . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.
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STM32F103xC, STM32F103xD, STM32F103xE Contents 2.3.29 Serial wire JTAG debug port (SWJ-DP) . . . . . . . . . . . . . . . . . . . . . . . . . 24 2.3.30 Embedded Trace Macrocell™ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3 Pinouts and pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 4 Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 5 Electrical characteristics . . . . . . . . . . . .
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Contents 6 STM32F103xC, STM32F103xD, STM32F103xE 5.3.20 DAC electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 5.3.21 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 6.1 LFBGA144 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 6.2 LFBGA100 package information . . . . . . . . .
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STM32F103xC, STM32F103xD, STM32F103xE List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. Table 43. Device summary . . .
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List of tables Table 44. Table 45. Table 46. Table 47. Table 48. Table 49. Table 50. Table 51. Table 52. Table 53. Table 54. Table 55. Table 56. Table 57. Table 58. Table 59. Table 60. Table 61. Table 62. Table 63. Table 64. Table 65. Table 66. Table 67. Table 68. Table 69. Table 70. Table 71. Table 72. Table 73. Table 74. Table 75. 6/143 STM32F103xC, STM32F103xD, STM32F103xE Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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STM32F103xC, STM32F103xD, STM32F103xE List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Figure 38. Figure 39.
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List of figures Figure 40. Figure 41. Figure 42. Figure 43. Figure 44. Figure 45. Figure 46. Figure 47. Figure 48. Figure 49. Figure 50. Figure 51. Figure 52. Figure 53. Figure 54. Figure 55. Figure 56. Figure 57. Figure 58. Figure 59. Figure 60. Figure 61. Figure 62. Figure 63. Figure 64. Figure 65. Figure 66. Figure 67. Figure 68. Figure 69. Figure 70. Figure 71. Figure 72. Figure 73. Figure 74. Figure 75. Figure 76. Figure 77. Figure 78. Figure 79.
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STM32F103xC, STM32F103xD, STM32F103xE 1 Introduction Introduction This datasheet provides the ordering information and mechanical device characteristics of the STM32F103xC, STM32F103xD and STM32F103xE high-density performance line microcontrollers. For more details on the whole STMicroelectronics STM32F103xC/D/E family, please refer to Section 2.2: Full compatibility throughout the family. The high-density STM32F103xC/D/E datasheet should be read in conjunction with the STM32F10xxx reference manual.
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Description 2 STM32F103xC, STM32F103xD, STM32F103xE Description The STM32F103xC, STM32F103xD and STM32F103xE performance line family incorporates the high-performance Arm® Cortex®-M3 32-bit RISC core operating at a 72 MHz frequency, high-speed embedded memories (Flash memory up to 512 Kbytes and SRAM up to 64 Kbytes), and an extensive range of enhanced I/Os and peripherals connected to two APB buses.
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STM32F103xC, STM32F103xD, STM32F103xE 2.1 Description Device overview The STM32F103xC/D/E high-density performance line family offers devices in six different package types: from 64 pins to 144 pins. Depending on the device chosen, different sets of peripherals are included, the description below gives an overview of the complete range of peripherals proposed in this family. Figure 1 shows the general block diagram of the device family. Table 2.
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Description STM32F103xC, STM32F103xD, STM32F103xE Figure 1. STM32F103xC, STM32F103xD and STM32F103xE performance line block diagram 37 *4!' 4RACE TRIG 4RACE CONTROLLER 0BUS &LASH OBL INTERFACE .*4234 *4$) *4#+ 37#,+ *4-3 37$)/ *4$/ AS !& 6$$ 40)5 )BUS #ORTEX - #05 &MAX -(Z $BUS 3YSTEM .6)# "US -ATRIX 42!#%#,+ 42!#%$; = AS !3 6$$ &LASH +BYTES BIT 32! +" 6$$! 2# -(Z '0 $-! !; = $; = #,+ ./% .7% .%; = .",; = .7!)4 ., OR .
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STM32F103xC, STM32F103xD, STM32F103xE Description Figure 2. Clock tree )/,7)&/. WR )ODVK SURJUDPPLQJ LQWHUIDFH 86% 3UHVFDOHU 86%&/. WR 86% LQWHUIDFH 0+] , 6 &/. 3HULSKHUDO FORFN HQDEOH 0+] +6, 5& , 6 &/. 6: 3//08/ +6, [ [ [ [ 3// 6<6&/. $+% 3UHVFDOHU 0+] PD[ 3//&/. $3% 3UHVFDOHU WR 57& /6( 57&&/. WR ,QGHSHQGHQW :DWFKGRJ ,:'* /6, $'& 3UHVFDOHU 57&6(/> @ /6, 5& N+] 0+] PD[ 3&/.
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Description 2.2 STM32F103xC, STM32F103xD, STM32F103xE Full compatibility throughout the family The STM32F103xC/D/E is a complete family whose members are fully pin-to-pin, software and feature compatible. In the reference manual, the STM32F103x4 and STM32F103x6 are identified as low-density devices, the STM32F103x8 and STM32F103xB are referred to as medium-density devices and the STM32F103xC, STM32F103xD and STM32F103xE are referred to as high-density devices.
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STM32F103xC, STM32F103xD, STM32F103xE 2.3 Overview 2.3.1 Arm® Cortex®-M3 core with embedded Flash and SRAM Description The Arm Cortex®-M3 processor is the latest generation of Arm processors for embedded systems. It has been developed to provide a low-cost platform that meets the needs of MCU implementation, with a reduced pin count and low-power consumption, while delivering outstanding computational performance and an advanced system response to interrupts.
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Description 2.3.6 STM32F103xC, STM32F103xD, STM32F103xE LCD parallel interface The FSMC can be configured to interface seamlessly with most graphic LCD controllers. It supports the Intel 8080 and Motorola 6800 modes, and is flexible enough to adapt to specific LCD interfaces. This LCD parallel interface capability makes it easy to build costeffective graphic applications using LCD modules with embedded controllers or highperformance solutions using external controllers with dedicated acceleration. 2.3.
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STM32F103xC, STM32F103xD, STM32F103xE 2.3.10 Description Boot modes At startup, boot pins are used to select one of three boot options: • Boot from user Flash: you have an option to boot from any of two memory banks. By default, boot from Flash memory bank 1 is selected. You can choose to boot from Flash memory bank 2 by setting a bit in the option bytes. • Boot from system memory • Boot from embedded SRAM The boot loader is located in system memory.
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Description 2.3.14 STM32F103xC, STM32F103xD, STM32F103xE Low-power modes The STM32F103xC, STM32F103xD and STM32F103xE performance line supports three low-power modes to achieve the best compromise between low-power consumption, short startup time and available wakeup sources: • Sleep mode In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can wake up the CPU when an interrupt/event occurs.
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STM32F103xC, STM32F103xD, STM32F103xE Description periodic interrupt. It is clocked by a 32.768 kHz external crystal, resonator or oscillator, the internal low-power RC oscillator or the high-speed external clock divided by 128. The internal low-speed RC has a typical frequency of 40 kHz. The RTC can be calibrated using an external 512 Hz output to compensate for any natural quartz deviation.
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Description STM32F103xC, STM32F103xD, STM32F103xE Advanced-control timers (TIM1 and TIM8) The two advanced-control timers (TIM1 and TIM8) can each be seen as a three-phase PWM multiplexed on 6 channels. They have complementary PWM outputs with programmable inserted dead-times. They can also be seen as a complete general-purpose timer.
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STM32F103xC, STM32F103xD, STM32F103xE Description the main clock. It has an early warning interrupt capability and the counter can be frozen in debug mode. SysTick timer This timer is dedicated to real-time operating systems, but could also be used as a standard down counter. It features: 2.3.18 • A 24-bit down counter • Autoreload capability • Maskable system interrupt generation when the counter reaches 0.
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Description STM32F103xC, STM32F103xD, STM32F103xE mode, the master clock can be output to the external DAC/CODEC at 256 times the sampling frequency. 2.3.22 SDIO An SD/SDIO/MMC host interface is available, that supports MultiMediaCard System Specification Version 4.2 in three different databus modes: 1-bit (default), 4-bit and 8-bit. The interface allows data transfer at up to 48 MHz in 8-bit mode, and is compliant with SD Memory Card Specifications Version 2.0. The SDIO Card Specification Version 2.
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STM32F103xC, STM32F103xD, STM32F103xE Description The ADC can be served by the DMA controller. An analog watchdog feature allows very precise monitoring of the converted voltage of one, some or all selected channels. An interrupt is generated when the converted voltage is outside the programmed thresholds.
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Description 2.3.28 STM32F103xC, STM32F103xD, STM32F103xE Temperature sensor The temperature sensor has to generate a voltage that varies linearly with temperature. The conversion range is between 2 V < VDDA < 3.6 V. The temperature sensor is internally connected to the ADC1_IN16 input channel which is used to convert the sensor output voltage into a digital value. 2.3.
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STM32F103xC, STM32F103xD, STM32F103xE 3 Pinouts and pin descriptions Pinouts and pin descriptions Figure 3.
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Pinouts and pin descriptions STM32F103xC, STM32F103xD, STM32F103xE Figure 4.
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STM32F103xC, STM32F103xD, STM32F103xE Pinouts and pin descriptions 6$$? 633? 0% 0% 0" 0" "//4 0" 0" 0" 0" 0" 0' 6$$? 633? 0' 0' 0' 0' 0' 0' 0$ 0$ 6$$? 633? 0$ 0$ 0$ 0$ 0$ 0$ 0# 0# 0# 0! 0! Figure 5.
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Pinouts and pin descriptions STM32F103xC, STM32F103xD, STM32F103xE 6$$? 633? 0% 0% 0" 0" "//4 0" 0" 0" 0" 0" 0$ 0$ 0$ 0$ 0$ 0$ 0$ 0$ 0# 0# 0# 0! 0! Figure 6. STM32F103xC/D/E performance line LQFP100 pinout ,1&0 6$$? 633? .
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STM32F103xC, STM32F103xD, STM32F103xE Pinouts and pin descriptions s ͺϯ s^^ͺϯ W ϵ W ϴ KK d Ϭ W ϳ W ϲ W ϱ W ϰ W ϯ W Ϯ W ϭϮ W ϭϭ W ϭϬ W ϭϱ W ϭϰ Figure 7.
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Pinouts and pin descriptions STM32F103xC, STM32F103xD, STM32F103xE Figure 8.
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STM32F103xC, STM32F103xD, STM32F103xE Pinouts and pin descriptions Table 5.
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Pinouts and pin descriptions STM32F103xC, STM32F103xD, STM32F103xE Table 5.
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STM32F103xC, STM32F103xD, STM32F103xE Pinouts and pin descriptions Table 5.
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Pinouts and pin descriptions STM32F103xC, STM32F103xD, STM32F103xE Table 5.
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STM32F103xC, STM32F103xD, STM32F103xE Pinouts and pin descriptions Table 5.
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Pinouts and pin descriptions STM32F103xC, STM32F103xD, STM32F103xE Table 5.
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STM32F103xC, STM32F103xD, STM32F103xE Pinouts and pin descriptions 5. PC13, PC14 and PC15 are supplied through the power switch. Since the switch only sinks a limited amount of current (3 mA), the use of GPIOs PC13 to PC15 in output mode is limited: the speed should not exceed 2 MHz with a maximum load of 30 pF and these IOs must not be used as a current source (e.g. to drive an LED). 6. Main function after the first backup domain power-up.
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Pinouts and pin descriptions STM32F103xC, STM32F103xD, STM32F103xE Table 6.
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STM32F103xC, STM32F103xD, STM32F103xE Pinouts and pin descriptions Table 6.
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Memory mapping 4 STM32F103xC, STM32F103xD, STM32F103xE Memory mapping The memory map is shown in Figure 9. Figure 9.
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STM32F103xC, STM32F103xD, STM32F103xE Electrical characteristics 5 Electrical characteristics 5.1 Parameter conditions Unless otherwise specified, all voltages are referenced to VSS. 5.1.
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Electrical characteristics 5.1.6 STM32F103xC, STM32F103xD, STM32F103xE Power supply scheme Figure 12.
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STM32F103xC, STM32F103xD, STM32F103xE 5.2 Electrical characteristics Absolute maximum ratings Stresses above the absolute maximum ratings listed in Table 7: Voltage characteristics, Table 8: Current characteristics, and Table 9: Thermal characteristics may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Table 7.
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Electrical characteristics STM32F103xC, STM32F103xD, STM32F103xE Table 9. Thermal characteristics Symbol TSTG TJ Ratings Storage temperature range Maximum junction temperature 5.3 Operating conditions 5.3.1 General operating conditions Value Unit –65 to +150 °C 150 °C Table 10.
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STM32F103xC, STM32F103xD, STM32F103xE 5.3.2 Electrical characteristics Operating conditions at power-up / power-down The parameters given in Table 11 are derived from tests performed under the ambient temperature condition summarized in Table 10. Table 11. Operating conditions at power-up / power-down Symbol Parameter VDD rise time rate tVDD 5.3.
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Electrical characteristics 5.3.4 STM32F103xC, STM32F103xD, STM32F103xE Embedded reference voltage The parameters given in Table 13 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 10. Table 13. Embedded internal reference voltage Symbol Conditions Min Typ –40 °C < TA < +105 °C 1.16 1.20 1.26 –40 °C < TA < +85 °C 1.16 1.20 1.24 ADC sampling time when TS_vrefint(1) reading the internal reference voltage - - 5.1 17.
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STM32F103xC, STM32F103xD, STM32F103xE Electrical characteristics Table 14. Maximum current consumption in Run mode, code with data processing running from Flash Max(1) Symbol Parameter Conditions fHCLK TA = 105 °C 72 MHz 69 70 48 MHz 50 50.5 36 MHz 39 39.5 24 MHz 27 28 16 MHz 20 20.5 8 MHz 11 11.5 72 MHz 37 37.5 48 MHz 28 28.5 External clock(2), all 36 MHz peripherals disabled 24 MHz 22 22.5 16.5 17 16 MHz 12.
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Electrical characteristics STM32F103xC, STM32F103xD, STM32F103xE Figure 14. Typical current consumption in Run mode versus frequency (at 3.6 V) code with data processing running from RAM, peripherals enabled #ONSUMPTION M! -(Z -(Z -(Z -(Z -(Z -(Z 4EMPERATURE # AI Figure 15. Typical current consumption in Run mode versus frequency (at 3.
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STM32F103xC, STM32F103xD, STM32F103xE Electrical characteristics Table 16. Maximum current consumption in Sleep mode, code running from Flash or RAM Max(1) Symbol Parameter Conditions External clock(2), all peripherals enabled IDD Supply current in Sleep mode External clock(2), all peripherals disabled fHCLK Unit TA = 85 °C TA = 105 °C 72 MHz 45 46 48 MHz 31 32 36 MHz 24 25 24 MHz 17 17.5 16 MHz 12.5 13 8 MHz 8 8 72 MHz 8.5 9 48 MHz 7 7.5 36 MHz 6 6.5 24 MHz 5 5.
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Electrical characteristics STM32F103xC, STM32F103xD, STM32F103xE Table 17. Typical and maximum current consumptions in Stop and Standby modes Typ(1) Symbol Parameter Supply current in Stop mode IDD Supply current in Standby mode Backup domain IDD_VBAT supply current Conditions VDD/VBAT VDD/VBAT VDD/VBAT TA = = 2.0 V = 2.4 V = 3.3 V 85 °C TA = 105 °C Regulator in run mode, lowspeed and high-speed internal RC oscillators and high-speed oscillator OFF (no independent watchdog) - 34.
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STM32F103xC, STM32F103xD, STM32F103xE Electrical characteristics Figure 16. Typical current consumption on VBAT with RTC on vs. temperature at different VBAT values 9 9 9 9 9 ± 7HPSHUDWXUH & DL Figure 17.
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Electrical characteristics STM32F103xC, STM32F103xD, STM32F103xE Figure 18. Typical current consumption in Stop mode with regulator in low-power mode versus temperature at different VDD values #ONSUMPTION ȝ! 6 6 6 6 6 # # # # 4EMPERATURE # AI Figure 19.
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STM32F103xC, STM32F103xD, STM32F103xE Electrical characteristics Typical current consumption The MCU is placed under the following conditions: • All I/O pins are in input mode with a static value at VDD or VSS (no load). • All peripherals are disabled except if it is explicitly mentioned. • The Flash access time is adjusted to fHCLK frequency (0 wait state from 0 to 24 MHz, 1 wait state from 24 to 48 MHZ and 2 wait states above).
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Electrical characteristics STM32F103xC, STM32F103xD, STM32F103xE 2. Add an additional power consumption of 0.8 mA per ADC for the analog part. In applications, this consumption occurs only while the ADC is on (ADON bit is set in the ADC_CR2 register). 3. External clock is 8 MHz and PLL is on when fHCLK > 8 MHz. Table 19. Typical current consumption in Sleep mode, code running from Flash or RAM Typ(1) Symbol Parameter Conditions 29.5 6.4 48 MHz 20 4.6 36 MHz 15.1 3.6 24 MHz 10.4 2.
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STM32F103xC, STM32F103xD, STM32F103xE Electrical characteristics On-chip peripheral current consumption The current consumption of the on-chip peripherals is given in Table 20.
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Electrical characteristics STM32F103xC, STM32F103xD, STM32F103xE Table 20.
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STM32F103xC, STM32F103xD, STM32F103xE Electrical characteristics Table 20. Peripheral current consumption (continued) Current consumption Peripheral APB2 (up to 72 MHz) APB2-Bridge 4,17 GPIOA 8,47 GPIOB 8,47 GPIOC 6,53 GPIOD 8,47 GPIOE 6,53 GPIOF 6,53 GPIOG 6,11 SPI1 4,72 USART1 12,50 TIM1 22,92 TIM8 22,92 (4) ADC1 17,32 ADC2(4) 15,18 ADC3(4) 14,82 Unit μA/MHz 1. The BusMatrix is automatically active when at least one master is ON. (CPU, DMA1 or DMA2). 2.
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Electrical characteristics 5.3.6 STM32F103xC, STM32F103xD, STM32F103xE External clock source characteristics High-speed external user clock generated from an external source The characteristics given in Table 21 result from tests performed using an high-speed external clock source, and under ambient temperature and supply voltage conditions summarized in Table 10. Table 21.
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STM32F103xC, STM32F103xD, STM32F103xE Electrical characteristics Figure 20. High-speed external clock source AC timing diagram 6(3%( 6(3%, TR (3% TF (3% T7 (3% /3#?). ), T7 (3% T 4(3% %XTERNAL CLOCK SOURCE F(3%?EXT 34- & AI Figure 21.
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Electrical characteristics STM32F103xC, STM32F103xD, STM32F103xE High-speed external clock generated from a crystal/ceramic resonator The high-speed external (HSE) clock can be supplied with a 4 to 16 MHz crystal/ceramic resonator oscillator. All the information given in this paragraph are based on characterization results obtained with typical external components specified in Table 23.
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STM32F103xC, STM32F103xD, STM32F103xE Electrical characteristics Low-speed external clock generated from a crystal/ceramic resonator The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal/ceramic resonator oscillator. All the information given in this paragraph are based on characterization results obtained with typical external components specified in Table 24.
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Electrical characteristics STM32F103xC, STM32F103xD, STM32F103xE Figure 23. Typical application with a 32.768 kHz crystal 5HVRQDWRU ZLWK LQWHJUDWHG FDSDFLWRUV &/ I/6( 26& B,1 %LDV 5) FRQWUROOHG JDLQ N+ ] UHVRQDWRU 26& B28 7 &/ 670 ) DL 5.3.7 Internal clock source characteristics The parameters given in Table 25 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 10. High-speed internal (HSI) RC oscillator Table 25.
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STM32F103xC, STM32F103xD, STM32F103xE Electrical characteristics Low-speed internal (LSI) RC oscillator Table 26. LSI oscillator characteristics (1) Symbol fLSI(2) tsu(LSI) (3) IDD(LSI)(3) Parameter Min Typ Max Unit 30 40 60 kHz LSI oscillator startup time - - 85 µs LSI oscillator power consumption - 0.65 1.2 µA Frequency 1. VDD = 3 V, TA = –40 to 105 °C unless otherwise specified. 2. Guaranteed by characterization results. 3. Guaranteed by design.
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Electrical characteristics 5.3.8 STM32F103xC, STM32F103xD, STM32F103xE PLL characteristics The parameters given in Table 28 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 10. Table 28. PLL characteristics Value Symbol Parameter Unit Min Typ Max(1) PLL input clock(2) 1 8.
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STM32F103xC, STM32F103xD, STM32F103xE Electrical characteristics Table 30. Flash memory endurance and data retention Value Symbol NEND tRET Parameter Endurance Data retention Conditions Min(1) TA = -40 to +85 °C (6 suffix versions) TA = -40 to +105 °C (7 suffix versions) 10 1 kcycle(2) at TA = 85 °C 30 1 kcycle (2) 10 kcycles at TA = 105 °C 10 (2) 20 at TA = 55 °C Unit kcycles Years 1. Guaranteed by characterization results. 2. Cycling performed over the whole temperature range.
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Electrical characteristics 5.3.10 STM32F103xC, STM32F103xD, STM32F103xE FSMC characteristics Asynchronous waveforms and timings Figure 24 through Figure 27 represent asynchronous waveforms and Table 31 through Table 34 provide the corresponding timings. The results shown in these tables are obtained with the following FSMC configuration: • AddressSetupTime = 0 • AddressHoldTime = 1 • DataSetupTime = 1 Figure 24.
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STM32F103xC, STM32F103xD, STM32F103xE Electrical characteristics Table 31. Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings(1) Symbol Parameter Min tw(NE) FSMC_NE low time tv(NOE_NE) FSMC_NEx low to FSMC_NOE low tw(NOE) FSMC_NOE low time th(NE_NOE) FSMC_NOE high to FSMC_NE high hold time tv(A_NE) FSMC_NEx low to FSMC_A valid th(A_NOE) Address hold time after FSMC_NOE high tv(BL_NE) 5tHCLK – 1.5 Max 5tHCLK + 2 Unit ns 0.5 1.5 ns 5tHCLK – 1.5 5tHCLK + 1.5 ns –1.
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Electrical characteristics STM32F103xC, STM32F103xD, STM32F103xE Table 32. Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings(1)(2) Symbol Parameter Min Max Unit tw(NE) FSMC_NE low time 3tHCLK – 1 3tHCLK + 2 ns tv(NWE_NE) FSMC_NEx low to FSMC_NWE low tHCLK – 0.5 tHCLK + 1.
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STM32F103xC, STM32F103xD, STM32F103xE Electrical characteristics Table 33. Asynchronous multiplexed PSRAM/NOR read timings(1)(2) Symbol Parameter Min Max Unit tw(NE) FSMC_NE low time 7tHCLK – 2 7tHCLK + 2 ns tv(NOE_NE) FSMC_NEx low to FSMC_NOE low 3tHCLK – 0.5 3tHCLK + 1.
PAGE 70
Electrical characteristics STM32F103xC, STM32F103xD, STM32F103xE Figure 27. Asynchronous multiplexed PSRAM/NOR write waveforms WZ 1( )60&B1([ )60&B12( WY 1:(B1( WZ 1:( W K 1(B1:( )60&B1:( WK $B1:( WY $B1( )60&B$> @ $GGUHVV WY %/B1( WK %/B1:( )60&B1%/> @ 1%/ W Y $B1( W Y 'DWDB1$'9 $GGUHVV )60&B$'> @ W Y 1$'9B1( WK 'DWDB1:( 'DWD WK $'B1$'9 WZ 1$'9 )60&B1$'9 DL % Table 34.
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STM32F103xC, STM32F103xD, STM32F103xE Electrical characteristics Synchronous waveforms and timings Figure 28 through Figure 31 represent synchronous waveforms and Table 36 through Table 38 provide the corresponding timings.
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Electrical characteristics STM32F103xC, STM32F103xD, STM32F103xE Table 35. Synchronous multiplexed NOR/PSRAM read timings(1)(2) Symbol Parameter Max Unit 27.7 - ns tw(CLK) FSMC_CLK period td(CLKL-NExL) FSMC_CLK low to FSMC_NEx low (x = 0...2) - 1.5 ns td(CLKL-NExH) FSMC_CLK low to FSMC_NEx high (x = 0...2) 2 - ns td(CLKL-NADVL) FSMC_CLK low to FSMC_NADV low - 4 ns td(CLKL-NADVH) FSMC_CLK low to FSMC_NADV high 5 - ns td(CLKL-AV) FSMC_CLK low to FSMC_Ax valid (x = 16...
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STM32F103xC, STM32F103xD, STM32F103xE Electrical characteristics Figure 29. Synchronous multiplexed PSRAM write timings "53452. TW #,+ TW #,+ &3-#?#,+ $ATA LATENCY TD #,+, .%X, TD #,+, .%X( &3-#?.%X TD #,+, .!$6, TD #,+, .!$6( &3-#?.!$6 TD #,+, !6 TD #,+, !)6 &3-#?!; = TD #,+, .7%, TD #,+, .7%( &3-#?.7% TD #,+, !$)6 TD #,+, $ATA TD #,+, $ATA TD #,+, !$6 !$; = &3-#?!$; = $ $ &3-#?.7!)4 7!)4#&' B 7!)40/, B TSU .7!)46 #,+( TH #,+( .7!)46 TD #,+, .",( &3-#?.
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Electrical characteristics STM32F103xC, STM32F103xD, STM32F103xE Table 36. Synchronous multiplexed PSRAM write timings(1)(2) Symbol Parameter Max Unit 27.7 - ns tw(CLK) FSMC_CLK period td(CLKL-NExL) FSMC_CLK low to FSMC_Nex low (x = 0...2) - 2 ns td(CLKL-NExH) FSMC_CLK low to FSMC_NEx high (x = 0...2) 2 - ns td(CLKL-NADVL) FSMC_CLK low to FSMC_NADV low - 4 ns td(CLKL-NADVH) FSMC_CLK low to FSMC_NADV high 5 - ns td(CLKL-AV) FSMC_CLK low to FSMC_Ax valid (x = 16...
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STM32F103xC, STM32F103xD, STM32F103xE Electrical characteristics Figure 30. Synchronous non-multiplexed NOR/PSRAM read timings "53452. TW #,+ TW #,+ &3-#?#,+ TD #,+, .%X, TD #,+, .%X( $ATA LATENCY &3-#?.%X TD #,+, .!$6, TD #,+, .!$6( &3-#?.!$6 TD #,+, !)6 TD #,+, !6 &3-#?!; = TD #,+( ./%, TD #,+, ./%( &3-#?./% TSU $6 #,+( TH #,+( $6 TSU $6 #,+( &3-#?$; = $ TSU .7!)46 #,+( TH #,+( $6 $ $ TH #,+( .7!)46 &3-#?.7!)4 7!)4#&' B 7!)40/, B TSU .7!)46 #,+( T H #,+( .
PAGE 76
Electrical characteristics STM32F103xC, STM32F103xD, STM32F103xE Figure 31. Synchronous non-multiplexed PSRAM write timings %867851 WZ &/. WZ &/. )60&B&/. 'DWD ODWHQF\ WG &/./ 1([/ W G &/./ 1([+ )60&B1([ WG &/./ 1$'9/ WG &/./ 1$'9+ )60&B1$'9 WG &/./ $,9 WG &/./ $9 )60&B$> @ WG &/./ 12(+ WG &/.+ 12(/ )60&B12( WG &/./ $',9 WVX $'9 &/.+ WG &/./ $'9 )60&B$'> @ $'> @ WK &/.+ $'9 WVX $'9 &/.+ ' WVX 1:$,79 &/.+ WK &/.+ $'9 ' WK &/.
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STM32F103xC, STM32F103xD, STM32F103xE Electrical characteristics PC Card/CompactFlash controller waveforms and timings Figure 32 through Figure 37 represent synchronous waveforms and Table 39 provides the corresponding timings. The results shown in this table are obtained with the following FSMC configuration: • COM.FSMC_SetupTime = 0x04; • COM.FSMC_WaitSetupTime = 0x07; • COM.FSMC_HoldSetupTime = 0x04; • COM.FSMC_HiZSetupTime = 0x00; • ATT.FSMC_SetupTime = 0x04; • ATT.
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Electrical characteristics STM32F103xC, STM32F103xD, STM32F103xE Figure 33.
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STM32F103xC, STM32F103xD, STM32F103xE Electrical characteristics Figure 34. PC Card/CompactFlash controller waveforms for attribute memory read access )60&B1&( B WY 1&( B $ WK 1&( B $, )60&B1&( B +LJK )60&B$> @ )60&B1,2:5 )60&B1,25' WG 15(* 1&( B WK 1&( B 15(* )60&B15(* )60&B1:( WG 1&( B 12( WZ 12( WG 12( 1&( B )60&B12( WVX ' 12( WK 12( ' )60&B'> @ DL E 1. Only data bits 0...7 are read (bits 8...15 are disregarded).
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Electrical characteristics STM32F103xC, STM32F103xD, STM32F103xE Figure 35. PC Card/CompactFlash controller waveforms for attribute memory write access )60&B1&( B )60&B1&( B +LJK WY 1&( B $ WK 1&( B $, )60&B$> @ )60&B1,2:5 )60&B1,25' WG 15(* 1&( B WK 1&( B 15(* )60&B15(* WG 1&( B 1:( WZ 1:( )60&B1:( WG 1:( 1&( B )60&B12( WY 1:( ' )60&B'> @ DL E 1. Only data bits 0...7 are driven (bits 8...15 remains HiZ). Figure 36.
PAGE 81
STM32F103xC, STM32F103xD, STM32F103xE Electrical characteristics Figure 37. PC Card/CompactFlash controller waveforms for I/O space write access )60&B1&( B )60&B1&( B WY 1&([ $ WK 1&( B $, )60&B$> @ )60&B15(* )60&B1:( )60&B12( )60&B1,25' WG 1&( B 1,2:5 WZ 1,2:5 )60&B1,2:5 $77[+,= WY 1,2:5 ' WK 1,2:5 ' )60&B'> @ DL F Table 39.
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Electrical characteristics STM32F103xC, STM32F103xD, STM32F103xE Table 39.
PAGE 83
STM32F103xC, STM32F103xD, STM32F103xE Electrical characteristics NAND controller waveforms and timings Figure 38 through Figure 41 represent synchronous waveforms and Table 39 provides the corresponding timings. The results shown in this table are obtained with the following FSMC configuration: • COM.FSMC_SetupTime = 0x01; • COM.FSMC_WaitSetupTime = 0x03; • COM.FSMC_HoldSetupTime = 0x02; • COM.FSMC_HiZSetupTime = 0x01; • ATT.FSMC_SetupTime = 0x01; • ATT.FSMC_WaitSetupTime = 0x03; • ATT.
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Electrical characteristics STM32F103xC, STM32F103xD, STM32F103xE Figure 39. NAND controller waveforms for write access )60&B1&([ $/( )60&B$ &/( )60&B$ WG $/( 1:( WK 1:( $/( )60&B1:( )60&B12( 15( WK 1:( ' WY 1:( ' )60&B'> @ AI C Figure 40.
PAGE 85
STM32F103xC, STM32F103xD, STM32F103xE Electrical characteristics Figure 41. NAND controller waveforms for common memory write access )60&B1&([ /RZ $/( )60&B$ &/( )60&B$ WG $/( 1:( WZ 1:( WK 1:( $/( )60&B1:( )60&B12( WG ' 1:( WY 1:( ' WK 1:( ' )60&B'> @ DL E Table 40.
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Electrical characteristics 5.3.11 STM32F103xC, STM32F103xD, STM32F103xE EMC characteristics Susceptibility tests are performed on a sample basis during device characterization. Functional EMS (electromagnetic susceptibility) While a simple application is executed on the device (toggling 2 LEDs through I/O ports). the device is stressed by two electromagnetic events until a failure occurs.
PAGE 87
STM32F103xC, STM32F103xD, STM32F103xE Electrical characteristics To complete these trials, ESD stress can be applied directly on the device, over the range of specification values. When unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note AN1015). Electromagnetic Interference (EMI) The electromagnetic field emitted by the device are monitored while a simple application is executed (toggling 2 LEDs through the I/O ports).
PAGE 88
Electrical characteristics STM32F103xC, STM32F103xD, STM32F103xE Table 44. Electrical sensitivities Symbol LU 5.3.13 Parameter Static latch-up class Conditions Class TA = +105 °C conforming to JESD78A II level A I/O current injection characteristics As a general rule, current injection to the I/O pins, due to external voltage below VSS or above VDD (for standard, 3 V-capable I/O pins) should be avoided during normal product operation.
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STM32F103xC, STM32F103xD, STM32F103xE 5.3.14 Electrical characteristics I/O port characteristics General input/output characteristics Unless otherwise specified, the parameters given in Table 46 are derived from tests performed under the conditions summarized in Table 10. All I/Os are CMOS and TTL compliant. Table 46.
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Electrical characteristics STM32F103xC, STM32F103xD, STM32F103xE Figure 42. Standard I/O input characteristics - CMOS port 6)( 6), 6 6 $$ 6 $$ NT 6 )( /3 STAN #- 7)(MIN )NPUT RANGE NOT GUARANTEED 6 6), $$ T 6 ), 6 $$ RD REQUIREMEN #-/3 STANDA 7),MAX 6 )( UIREME DARD REQ 6$$ 6 AI B Figure 43.
PAGE 91
STM32F103xC, STM32F103xD, STM32F103xE Electrical characteristics Figure 45.
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Electrical characteristics STM32F103xC, STM32F103xD, STM32F103xE Table 47.
PAGE 93
STM32F103xC, STM32F103xD, STM32F103xE Electrical characteristics Input/output AC characteristics The definition and values of input/output AC characteristics are given in Figure 46 and Table 48, respectively. Unless otherwise specified, the parameters given in Table 48 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 10. Table 48.
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Electrical characteristics STM32F103xC, STM32F103xD, STM32F103xE Figure 46. I/O AC characteristics definition (;7(51$/ 287387 21 &/ WU ,2 RXW WI ,2 RXW 7 0D[LPXP IUHTXHQF\ LV DFKLHYHG LI WU WI 7 DQG LI WKH GXW\ F\FOH LV ZKHQ ORDGHG E\ &/ VSHFLILHG LQ WKH WDEOH ³ , 2 $& FKDUDFWHULVWLFV´ 5.3.15 DL G NRST pin characteristics The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up resistor, RPU (see Table 46).
PAGE 95
STM32F103xC, STM32F103xD, STM32F103xE Electrical characteristics Figure 47. Recommended NRST pin protection 9'' ([WHUQDO UHVHW FLUFXLW 538 1567 ,QWHUQDO 5HVHW )LOWHU ) 670 ) DL F 1. The reset network protects the device against parasitic resets. 2. The user must ensure that the level on the NRST pin can go below the VIL(NRST) max level specified in Table 49. Otherwise the reset will not be taken into account by the device. 5.3.
PAGE 96
Electrical characteristics 5.3.17 STM32F103xC, STM32F103xD, STM32F103xE Communications interfaces I2C interface characteristics The STM32F103xC, STM32F103xD and STM32F103xESTM32F103xF and STM32F103xG performance line I2C interface meets the requirements of the standard I2C communication protocol with the following restrictions: the I/O pins SDA and SCL are mapped to are not “true” open-drain. When configured as open-drain, the PMOS connected between the I/O pin and VDD is disabled, but is still present.
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STM32F103xC, STM32F103xD, STM32F103xE Electrical characteristics Figure 48. I2C bus AC waveforms and measurement circuit 9''B, & 9''B, & 53 53 670 56 6'$ ,ð& EXV 56 6&/ 67$57 5(3($7(' 67$57 67$57 WVX 67$ 6'$ WI 6'$ WU 6'$ WK 67$ WVX 6'$ WK 6'$ WZ 6&// 6&/ WZ 6&/+ WU 6&/ WI 6&/ WZ 672 67$ 6 723 WVX 672 DL G 1. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD. 2. Rs: Series protection resistors. 3. Rp: Pull-up resistors. 4. VDD_I2C : I2C bus supply Table 52.
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Electrical characteristics STM32F103xC, STM32F103xD, STM32F103xE I2S - SPI characteristics Unless otherwise specified, the parameters given in Table 53 for SPI or in Table 54 for I2S are derived from tests performed under ambient temperature, fPCLKx frequency and VDD supply voltage conditions summarized in Table 10. Refer to Section 5.3.14: I/O port characteristics for more details on the input/output alternate function characteristics (NSS, SCK, MOSI, MISO for SPI and WS, CK, SD for I2S). Table 53.
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STM32F103xC, STM32F103xD, STM32F103xE Electrical characteristics Figure 49. SPI timing diagram - slave mode and CPHA = 0 Figure 50. SPI timing diagram - slave mode and CPHA = 1(1) 166 LQSXW 6&. LQSXW W68 166 &3+$ &32/ &3+$ &32/ WZ 6&.+ WZ 6&./ WK 62 WY 62 WD 62 0,62 287387 06% 287 %,7 287 WU 6&. WI 6&. WGLV 62 /6% 287 WK 6, WVX 6, 026, ,1387 WK 166 WF 6&. 06% ,1 %,7 ,1 /6% ,1 DL E 1. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD.
PAGE 100
Electrical characteristics STM32F103xC, STM32F103xD, STM32F103xE Figure 51. SPI timing diagram - master mode(1) +LJK 166 LQSXW 6&. 2XWSXW &3+$ &32/ 6&. 2XWSXW WF 6&. &3+$ &32/ &3+$ &32/ &3+$ &32/ WVX 0, 0,62 ,13 87 WZ 6&.+ WZ 6&./ 06% ,1 WU 6&. WI 6&. %,7 ,1 /6% ,1 WK 0, 026, 287387 06% 287 WY 02 % , 7 287 /6% 287 WK 02 DL F 1. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD.
PAGE 101
STM32F103xC, STM32F103xD, STM32F103xE Electrical characteristics Table 54. I2S characteristics Symbol DuCy(SCK) Parameter Conditions Min Max Unit 30 70 % 1.522 1.525 Slave mode 0 6.
PAGE 102
Electrical characteristics STM32F103xC, STM32F103xD, STM32F103xE Figure 52. I2S slave timing diagram (Philips protocol)(1) 1. Measurement points are done at CMOS levels: 0.3 × VDD and 0.7 × VDD. 2. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first byte. Figure 53. I2S master timing diagram (Philips protocol)(1) 1. Guaranteed by characterization results. 2. LSB transmit/receive of the previously transmitted byte.
PAGE 103
STM32F103xC, STM32F103xD, STM32F103xE Electrical characteristics SD/SDIO MMC card host interface (SDIO) characteristics Unless otherwise specified, the parameters given in Table 55 are derived from tests performed under ambient temperature, fPCLKx frequency and VDD supply voltage conditions summarized in Table 10. Refer to Section 5.3.14: I/O port characteristics for more details on the input/output alternate function characteristics (D[7:0], CMD, CK). Figure 54. SDIO high-speed mode Figure 55.
PAGE 104
Electrical characteristics STM32F103xC, STM32F103xD, STM32F103xE Table 55.
PAGE 105
STM32F103xC, STM32F103xD, STM32F103xE Electrical characteristics Table 57. USB DC electrical characteristics Symbol Parameter Conditions Min.(1) Max.(1) Unit 3.0(3) 3.6 V 0.2 - Input levels VDD VDI (4) USB operating voltage(2) - Differential input sensitivity I(USB_DP, USB_DM) VCM(4) Differential common mode range Includes VDI range 0.8 2.5 VSE(4) Single ended receiver threshold 1.3 2.0 - 0.3 2.8 3.6 - V Output levels VOL Static output level low RL of 1.5 kΩ to 3.
PAGE 106
Electrical characteristics 5.3.18 STM32F103xC, STM32F103xD, STM32F103xE CAN (controller area network) interface Refer to Section 5.3.14: I/O port characteristics for more details on the input/output alternate function characteristics (CAN_TX and CAN_RX). 5.3.19 12-bit ADC characteristics Unless otherwise specified, the parameters given in Table 59 are preliminary values derived from tests performed under ambient temperature, fPCLK2 frequency and VDDA supply voltage conditions summarized in Table 10.
PAGE 107
STM32F103xC, STM32F103xD, STM32F103xE 1. Electrical characteristics Guaranteed by characterization results. 2. Guaranteed by design. 3. VREF+ can be internally connected to VDDA and VREF- can be internally connected to VSSA, depending on the package. Refer to Section 3: Pinouts and pin descriptions for further details. 4. For external triggers, a delay of 1/fPCLK2 must be added to the latency specified in Table 59.
PAGE 108
Electrical characteristics STM32F103xC, STM32F103xD, STM32F103xE Table 62. ADC accuracy(1) (2)(3) Symbol Parameter Test conditions ET Total unadjusted error EO Offset error EG Gain error ED Differential linearity error EL Integral linearity error fPCLK2 = 56 MHz, fADC = 14 MHz, RAIN < 10 kΩ, VDDA = 2.4 V to 3.6 V Measurements made after ADC calibration Typ Max(4) ±2 ±5 ±1.5 ±2.5 ±1.5 ±3 ±1 ±2 ±1.5 ±3 Unit LSB 1. ADC DC accuracy values are measured after internal calibration. 2.
PAGE 109
STM32F103xC, STM32F103xD, STM32F103xE Electrical characteristics Figure 58. Typical connection diagram using the ADC 670 ) 9'' 5$,1 9$,1 6DPSOH DQG KROG $'& FRQYHUWHU 97 9 5$'& $,1[ &SDUDVLWLF 97 9 ELW FRQYHUWHU & $'& ,/ $ DL 1. Refer to Table 59 for the values of RAIN, RADC and CADC. 2. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the pad capacitance (roughly 7 pF).
PAGE 110
Electrical characteristics STM32F103xC, STM32F103xD, STM32F103xE Figure 60. Power supply and reference decoupling (VREF+ connected to VDDA) 670 ) [[ 95() 9''$ 6HH QRWH ) Q) 95()± 966$ 6HH QRWH DL 1. VREF+ and VREF– inputs are available only on 100-pin packages.
PAGE 111
STM32F103xC, STM32F103xD, STM32F103xE 5.3.20 Electrical characteristics DAC electrical specifications Table 63. DAC characteristics Symbol Parameter Min Typ Max Unit Comments - VDDA Analog supply voltage 2.4 - 3.6 V VREF+ Reference supply voltage 2.4 - 3.
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Electrical characteristics STM32F103xC, STM32F103xD, STM32F103xE Table 63. DAC characteristics (continued) Symbol Min Typ Max Unit Comments - - ±10 mV - - - ±3 LSB Given for the DAC in 10-bit at VREF+ = 3.6 V - - ±12 LSB Given for the DAC in 12-bit at VREF+ = 3.6 V - - ±0.
PAGE 113
STM32F103xC, STM32F103xD, STM32F103xE 5.3.21 Electrical characteristics Temperature sensor characteristics Table 64. TS characteristics Symbol Parameter Min Typ Max Unit - ±1 ±2 °C TL VSENSE linearity with temperature Avg_Slope Average slope 4.0 4.3 4.6 mV/°C V25 Voltage at 25 °C 1.34 1.43 1.52 V tSTART(1) Startup time 4 - 10 µs TS_temp(2)(1) ADC sampling time when reading the temperature - - 17.1 µs 1. Guaranteed by design. 2.
PAGE 114
Package information 6 STM32F103xC, STM32F103xD, STM32F103xE Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. 6.1 LFBGA144 package information Figure 62. LFBGA144 – 144-ball low profile fine pitch ball grid array, 10 x 10 mm, 0.
PAGE 115
STM32F103xC, STM32F103xD, STM32F103xE Package information Table 65. LFBGA144 – 144-ball low profile fine pitch ball grid array, 10 x 10 mm, 0.8 mm pitch, package mechanical data (continued) inches(1) millimeters Symbol Min Typ Max Typ Min Max b 0.350 0.400 0.450 0.0138 0.0157 0.0177 D 9.900 10.000 10.100 0.3898 0.3937 0.3976 D1 - 8.800 - - 0.3465 - E 9.900 10.000 10.100 0.3898 0.3937 0.3976 E1 - 8.800 - - 0.3465 - e - 0.800 - - 0.0315 - F - 0.
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Package information STM32F103xC, STM32F103xD, STM32F103xE Table 66. LFBGA144 recommended PCB design rules (0.8 mm pitch BGA) (continued) Dimension Recommended values UBM 0.350 mm Dsm 0.470 mm typ. (depends on the solder mask registration tolerance) Stencil opening 0.400 mm Stencil thickness Between 0.100 mm to 0.125 mm Pad trace width 0.120 mm Ball Diameter 0.
PAGE 117
STM32F103xC, STM32F103xD, STM32F103xE 6.2 Package information LFBGA100 package information Figure 65. LFBGA100 - 10 x 10 mm low profile fine pitch ball grid array package outline = 6HDWLQJ SODQH GGG = $ $ $ $ ( H ; $ EDOO $ EDOO LGHQWLILHU LQGH[ DUHD ) ( $ ) ' ' H < . E EDOOV HHH 0 = < ; III 0 = %27720 9,(: 723 9,(: + B0(B9 1. Drawing is not to scale. Table 67.
PAGE 118
Package information STM32F103xC, STM32F103xD, STM32F103xE Table 67. LFBGA100 - 10 x 10 mm low profile fine pitch ball grid array package mechanical data inches(1) millimeters Symbol Min Typ Max Min Typ Max eee - - 0.150 - - 0.0059 fff - - 0.080 - - 0.0031 1. Values in inches are converted from mm and rounded to 4 decimal digits. Figure 66. LFBGA100 – 100-ball low profile fine pitch ball grid array, 10 x 10 mm, 0.
PAGE 119
STM32F103xC, STM32F103xD, STM32F103xE Package information Device marking for LFBGA100 package The following figure gives an example of topside marking orientation versus ball A1 identifier location. Figure 67. LFBGA100 marking example (package top view) $GGLWLRQDO LQIRUPDWLRQ ; 3URGXFW LGHQWLILFDWLRQ 670 ) 9 + 'DWH FRGH < :: %DOO $ LQGHQWLILHU 06Y 9 1.
PAGE 120
Package information 6.3 STM32F103xC, STM32F103xD, STM32F103xE WLCSP64 package information Figure 68. WLCSP, 64-ball 4.466 × 4.395 mm, 0.500 mm pitch, wafer-level chip-scale package outline H EEE = ) * $ 'HWDLO $ H H + * ) H $ $ %XPS VLGH 6LGH YLHZ ; ' < %XPS $ HHH = ( E $ 2ULHQWDWLRQ UHIHUHQFH FFF GGG DDD = ; < = = 6HDWLQJ SODQH 'HWDLO $ URWDWHG [ :DIHU EDFN VLGH &5B0(B9 1. Drawing is not to scale. 2.
PAGE 121
STM32F103xC, STM32F103xD, STM32F103xE Package information Table 69. WLCSP, 64-ball 4.466 × 4.395 mm, 0.500 mm pitch, wafer-level chip-scale package mechanical data inches(1) millimeters Symbol Min b(2) 0.290 Typ 0.320 Max 0.350 Min Typ Max 0.0114 0.0126 0.0138 e - 0.500 - - 0.0197 - e1 - 3.500 - - 0.1378 - F - 0.447 - - 0.0176 - G - 0.483 - - 0.0190 - D 4.446 4.466 4.486 0.1750 0.1758 0.1766 E 4.375 4.395 4.415 0.1722 0.1730 0.1738 H - 0.250 - - 0.
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Package information STM32F103xC, STM32F103xD, STM32F103xE Table 70. WLCSP64 recommended PCB design rules (0.5 mm pitch) (continued) 6.4 Dimension Recommended values Stencil Thickness Between 100 µm to 125 µm Pad trace width 100 µm Ball Diameter 320 µm LQFP144 package information Figure 70. LQFP144 - 144-pin, 20 x 20 mm low-profile quad flat package outline 6($7,1* 3/$1( F $ $ $ & PP *$8*( 3/$1( ' / ' .
PAGE 123
STM32F103xC, STM32F103xD, STM32F103xE Package information Table 71. LQFP144 - 144-pin, 20 x 20 mm low-profile quad flat package mechanical data inches(1) millimeters Symbol Min Typ Max Min Typ Max A - - 1.600 - - 0.0630 A1 0.050 - 0.150 0.0020 - 0.0059 A2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.170 0.220 0.270 0.0067 0.0087 0.0106 c 0.090 - 0.200 0.0035 - 0.0079 D 21.800 22.000 22.200 0.8583 0.8661 0.8740 D1 19.800 20.000 20.200 0.7795 0.7874 0.
PAGE 124
Package information STM32F103xC, STM32F103xD, STM32F103xE Figure 71. LQFP144 - 144-pin,20 x 20 mm low-profile quad flat package recommended footprint DL H 1. Dimensions are expressed in millimeters.
PAGE 125
STM32F103xC, STM32F103xD, STM32F103xE Package information Device marking for LQFP144 package The following figure gives an example of topside marking orientation versus pin 1 identifier location. Figure 72. LQFP144 marking example (package top view) 2SWLRQDO JDWH PDUN 5HYLVLRQ FRGH 3URGXFW LGHQWLILFDWLRQ ; 670 ) =(7 'DWH FRGH < :: 3LQ LGHQWLILHU 06Y 9 1.
PAGE 126
Package information 6.5 STM32F103xC, STM32F103xD, STM32F103xE LQFP100 package information Figure 73. LQFP100 – 14 x 14 mm 100 pin low-profile quad flat package outline MM C ! ! ! 3%!4).' 0,!.% # '!5'% 0,!.% $ , $ ! + CCC # , $ 0). )$%.4)&)#!4)/. % % % B E ,?-%?6 1. Drawing is not to scale. Table 72.
PAGE 127
STM32F103xC, STM32F103xD, STM32F103xE Package information Table 72. LQPF100 – 14 x 14 mm 100-pin low-profile quad flat package mechanical data (continued) inches(1) millimeters Symbol Min Typ Max Min Typ Max E3 - 12.000 - - 0.4724 - e - 0.500 - - 0.0197 - L 0.450 0.600 0.750 0.0177 0.0236 0.0295 L1 - 1.000 - - 0.0394 - k 0° 3.5° 7° 0° 3.5° 7° ccc - - 0.08 - - 0.0031 1. Values in inches are converted from mm and rounded to 4 decimal digits. Figure 74.
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Package information STM32F103xC, STM32F103xD, STM32F103xE Device marking for LQFP100 package The following figure gives an example of topside marking orientation versus pin 1 identifier location. Figure 75. LQFP100 marking example (package top view) 2SWLRQDO JDWH PDUN 3URGXFW LGHQWLILFDWLRQ ^dDϯϮ&ϭϬϯ sϴdϲ 5HYLVLRQ FRGH y 'DWH FRGH z tt 3LQ LGHQWLILHU 06Y 9 1.
PAGE 129
STM32F103xC, STM32F103xD, STM32F103xE 6.6 Package information LQFP64 package information Figure 76. LQFP64 – 10 x 10 mm 64 pin low-profile quad flat package outline PP *$8*( 3/$1( F $ $ $ 6($7,1* 3/$1( & $ FFF & ' ' ' . / / ( ( ( E 3,1 ,'(17,),&$7,21 H :B0(B9 1. Drawing is not in scale. Table 73. LQFP64 – 10 x 10 mm 64 pin low-profile quad flat package mechanical data inches(1) millimeters Symbol Min Typ Max Min Typ Max A - - 1.
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Package information STM32F103xC, STM32F103xD, STM32F103xE Table 73. LQFP64 – 10 x 10 mm 64 pin low-profile quad flat package mechanical data (continued) inches(1) millimeters Symbol Min Typ Max Min Typ Max E3 - 7.500 - - 0.2953 - e - 0.500 - - 0.0197 - θ 0° 3.5° 7° 0° 3.5° 7° L 0.450 0.600 0.750 0.0177 0.0236 0.0295 L1 - 1.000 - - 0.0394 - ccc - - 0.080 - - 0.0031 1. Values in inches are converted from mm and rounded to 4 decimal digits. Figure 77.
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STM32F103xC, STM32F103xD, STM32F103xE Package information Device marking for LQFP64 package The following figure gives an example of topside marking orientation versus pin 1 identifier location. Figure 78. LQFP64 marking example (package top view) 5HYLVLRQ FRGH 3URGXFW LGHQWLILFDWLRQ ^dDϯϮ&ϭϬϯ Z dϲ z tt 3LQ LGHQWLILHU 'DWH FRGH 06Y 9 1.
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Package information 6.7 STM32F103xC, STM32F103xD, STM32F103xE Thermal characteristics The maximum chip junction temperature (TJmax) must never exceed the values given in Table 10: General operating conditions on page 44.
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STM32F103xC, STM32F103xD, STM32F103xE 6.7.2 Package information Selecting the product temperature range When ordering the microcontroller, the temperature range is specified in the ordering information scheme shown in Table 75: Ordering information scheme. Each temperature range suffix corresponds to a specific guaranteed ambient temperature at maximum dissipation and, to a specific maximum junction temperature.
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Package information STM32F103xC, STM32F103xD, STM32F103xE Using the values obtained in Table 74 TJmax is calculated as follows: – For LQFP100, 46 °C/W TJmax = 115 °C + (46 °C/W × 134 mW) = 115 °C + 6.2 °C = 121.2 °C This is within the range of the suffix 7 version parts (–40 < TJ < 125 °C). In this case, parts must be ordered at least with the temperature range suffix 7 (see Table 75: Ordering information scheme). Figure 79. LQFP100 PD max vs.
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STM32F103xC, STM32F103xD, STM32F103xE 7 Ordering information Ordering information Table 75.
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Revision history 8 STM32F103xC, STM32F103xD, STM32F103xE Revision history Table 76.Document revision history Date Revision 07-Apr-2008 1 Initial release. 2 Document status promoted from Target Specification to Preliminary Data. Section 1: Introduction and Section 2.2: Full compatibility throughout the family modified. Small text changes. Note 2 added in Table 2: STM32F103xC, STM32F103xD and STM32F103xE features and peripheral counts on page 11.
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STM32F103xC, STM32F103xD, STM32F103xE Revision history Table 76.Document revision history Date 21-Jul-2008 Revision Changes 3 Document status promoted from Preliminary Data to full datasheet. FSMC (flexible static memory controller) on page 22 modified. Number of complementary channels corrected in Figure 1: STM32F103xF, STM32F103xD and STM32F103xGSTM32F103xF and STM32F103xG performance line block diagram.
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Revision history STM32F103xC, STM32F103xD, STM32F103xE Table 76.Document revision history Date 12-Dec-2008 138/143 Revision Changes 4 Timers specified on page 1 (motor control capability mentioned). Section 2.2: Full compatibility throughout the family updated. Table 6: High-density timer feature comparison added. General-purpose timers (TIMx) and Advanced-control timers (TIM1 and TIM8) on page 27 updated.
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STM32F103xC, STM32F103xD, STM32F103xE Revision history Table 76.Document revision history Date 30-Mar-2009 Revision Changes 5 I/O information clarified on page 1. Figure 4: STM32F103xC and STM32F103xE performance line BGA100 ballout corrected. I/O information clarified on page 1.
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Revision history STM32F103xC, STM32F103xD, STM32F103xE Table 76.Document revision history Date 21-Jul-2009 24-Sep-2009 140/143 Revision Changes 6 Figure 1: STM32F103xC, STM32F103xD and STM32F103xE performance line block diagram updated. Note 5 updated and Note 4 added in Table 5: High-density STM32F103xC/D/E pin definitions. VRERINT and TCoeff added to Table 13: Embedded internal reference voltage. Table 16: Maximum current consumption in Sleep mode, code running from Flash or RAM modified.
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STM32F103xC, STM32F103xD, STM32F103xE Revision history Table 76.Document revision history Date 19-Apr-2011 30-Sept-2014 23-Feb-2015 Revision Changes 8 Updated package choice for 103Rx in Table 2 Updated footnotes below Table 7: Voltage characteristics on page 43 and Table 8: Current characteristics on page 43 Updated tw min in Table 21: High-speed external user clock characteristics on page 58 Updated startup time in Table 24: LSE oscillator characteristics (fLSE = 32.
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Revision history STM32F103xC, STM32F103xD, STM32F103xE Table 76.Document revision history Date 31-08-2015 26-Nov-2015 10-Jul-2018 142/143 Revision Changes 11 Replaced USBDP and USBDM by USB_DP and USB_DM in the whole document. Updated: – Introduction – Reference standard in Table 43: ESD absolute maximum ratings. – Updated IDDA description in Table 63: DAC characteristics.
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STM32F103xC, STM32F103xD, STM32F103xE IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement.