Datasheet

DocID14611 Rev 10 69/136
STM32F103xC, STM32F103xD, STM32F103xE Electrical characteristics
129
Synchronous waveforms and timings
Figure 28 through Figure 31 represent synchronous waveforms and Table 36 through
Table 38 provide the corresponding timings. The results shown in these tables are obtained
with the following FSMC configuration:
● BurstAccessMode = FSMC_BurstAccessMode_Enable;
● MemoryType = FSMC_MemoryType_CRAM;
● WriteBurst = FSMC_WriteBurst_Enable;
● CLKDivision = 1; (0 is not supported, see the STM32F10xxx reference manual)
● DataLatency = 1 for NOR Flash; DataLatency = 0 for PSRAM
Table 34.Asynchronous multiplexed PSRAM/NOR write timings
(1)(2)
1. C
L
= 15 pF.
2. Based on characterization, not tested in production.
Symbol Parameter Min Max Unit
t
w(NE)
FSMC_NE low time 5t
HCLK
– 1 5t
HCLK
+ 2 ns
t
v(NWE_NE)
FSMC_NEx low to FSMC_NWE low 2t
HCLK
2t
HCLK
+ 1 ns
t
w(NWE)
FSMC_NWE low time 2t
HCLK
– 1 2t
HCLK
+ 2 ns
t
h(NE_NWE)
FSMC_NWE high to FSMC_NE high hold time t
HCLK
– 1 - ns
t
v(A_NE)
FSMC_NEx low to FSMC_A valid - 7 ns
t
v(NADV_NE)
FSMC_NEx low to FSMC_NADV low 3 5 ns
t
w(NADV)
FSMC_NADV low time t
HCLK
– 1 t
HCLK
+ 1 ns
t
h(AD_NADV)
FSMC_AD (address) valid hold time after
FSMC_NADV high
t
HCLK
– 3 - ns
t
h(A_NWE)
Address hold time after FSMC_NWE high 4t
HCLK
-ns
t
v(BL_NE)
FSMC_NEx low to FSMC_BL valid - 1.6 ns
t
h(BL_NWE)
FSMC_BL hold time after FSMC_NWE high t
HCLK
– 1.5 - ns
t
v(Data_NADV)
FSMC_NADV high to Data valid - t
HCLK
+ 1.5 ns
t
h(Data_NWE)
Data hold time after FSMC_NWE high t
HCLK
– 5 - ns