Datasheet

DocID14611 Rev 10 131/136
STM32F103xC, STM32F103xD, STM32F103xE Revision history
135
21-Jul-2008 3
Document status promoted from Preliminary Data to full datasheet.
FSMC (flexible static memory controller) on page 22 modified.
Number of complementary channels corrected in Figure 1:
STM32F103xF, STM32F103xD and STM32F103xGSTM32F103xF and
STM32F103xG performance line block diagram.
Power supply supervisor on page 23 modified and V
DDA
added to
Table 14: General operating conditions on page 59.
Table notes revised in Section 5: Electrical characteristics.
Capacitance modified in Figure 12: Power supply scheme on page 57.
Table 60: SCL frequency (f
PCLK1
= 36 MHz.,V
DD
= 3.3 V) updated.
Table 61: SPI characteristics modified, t
h(NSS)
modified in Figure 49:
SPI timing diagram - slave mode and CPHA = 0 on page 123.
Minimum SDA and SCL fall time value for Fast mode removed from
Table 59: I
2
C characteristics on page 120, note 1 modified.
I
DD_VBAT
values and some I
DD
values with regulator in run mode added
to Table 21: Typical and maximum current consumptions in Stop and
Standby modes on page 68.
Table 34: Flash memory endurance and data retention on page 87
updated.
t
su(NSS)
modified in Table 61: SPI characteristics on page 122.
EO corrected in Table 70: ADC accuracy on page 132. Figure 58:
Typical connection diagram using the ADC on page 133 and note below
corrected.
Typical T
S_temp
value removed from Table 72: TS characteristics on
page 137.
Section 6.1: Package mechanical data on page 138 updated.
Small text changes.
Table 75.Document revision history
Date Revision Changes