Datasheet

ManualsBrandsST ManualsEmbedded Processors & ControllersMicrocontroller 32bit 384KB LQFP

This is information on a product in full production.

February 2015 DocID14611 Rev 10 1/136

STM32F103xC, STM32F103xD,

STM32F103xE

High-density performance line ARM

-based 32-bit MCU with 256 to 512KB

Flash, USB, CAN, 11 timers, 3 ADCs, 13 communication interfaces

Datasheet − production data

Features

• Core: ARM

32-bit Cortex

-M3 CPU

– 72 MHz maximum frequency, 1.25 DMIPS/MHz

(Dhrystone 2.1) performance at 0 wait state

memory access

– Single-cycle multiplication and hardware

division

• Memories

– 256 to 512 Kbytes of Flash memory

– up to 64 Kbytes of SRAM

– Flexible static memory controller with 4 Chip

Select. Supports Compact Flash,

SRAM,

PSRAM, NOR and NAND

memories

– LCD parallel interface, 8080/6800 modes

• Clock, reset and supply management

– 2.0 to 3.6 V application supply and I/Os

– POR, PDR, and programmable voltage detector

(PVD)

– 4-to-16 MHz crystal oscillator

– Internal 8 MHz factory-trimmed RC

– Internal 40 kHz RC with calibration

– 32 kHz oscillator for RTC with calibration

• Low power

– Sleep, Stop and Standby modes

–V

BAT

supply for RTC and backup registers

• 3 × 12-bit, 1 µs A/D converters (up to 21

channels)

– Conversion range: 0 to 3.6 V

– Triple-sample and hold capability

– Temperature sensor

• 2 × 12-bit D/A converters

• DMA: 12-channel DMA controller

– Supported peripherals: timers, ADCs, DAC,

SDIO, I

Ss, SPIs, I

Cs and USARTs

• Debug mode

– Serial wire debug (SWD) & JTAG interfaces

–Cortex

-M3 Embedded Trace Macrocell™

• Up to 112 fast I/O ports

– 51/80/112 I/Os, all mappable on 16 external

interrupt vectors and almost all 5 V-tolerant

• Up to 11 timers

– Up to four 16-bit timers, each with up to 4

IC/OC/PWM or pulse counter and quadrature

(incremental) encoder input

– 2 × 16-bit motor control PWM timers with dead-

time generation and emergency stop

– 2 × watchdog timers (Independent and Window)

– SysTick timer: a 24-bit downcounter

– 2 × 16-bit basic timers to drive the DAC

• Up to 13 communication interfaces

– Up to 2 × I

C interfaces (SMBus/PMBus)

– Up to 5 USARTs (ISO 7816 interface, LIN, IrDA

capability, modem control)

– Up to 3 SPIs (18 Mbit/s), 2 with I

S interface

multiplexed

– CAN interface (2.0B Active)

– USB 2.0 full speed interface

– SDIO interface

• CRC calculation unit, 96-bit unique ID

• ECOPACK

packages

Table 1.Device summary

Reference Part number

STM32F103xC

STM32F103RC STM32F103VC

STM32F103ZC

STM32F103xD

STM32F103RD STM32F103VD

STM32F103ZD

STM32F103xE

STM32F103RE STM32F103ZE

STM32F103VE

LQFP64 10 × 10 mm,

LQFP100 14 × 14 mm,

LQFP144 20 × 20 mm

LFBGA100 10 × 10 mm

LFBGA144 10 × 10 mm

WLCSP64

www.st.com

Summary of content (136 pages)

PAGE 1
STM32F103xC, STM32F103xD, STM32F103xE High-density performance line ARM®-based 32-bit MCU with 256 to 512KB Flash, USB, CAN, 11 timers, 3 ADCs, 13 communication interfaces Datasheet −production data Features • Core: ARM® 32-bit Cortex®-M3 CPU – – WLCSP64 72 MHz maximum frequency, 1.25 DMIPS/MHz (Dhrystone 2.
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Contents STM32F103xC, STM32F103xD, STM32F103xE Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2/136 2.1 Device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.2 Full compatibility throughout the family . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.
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STM32F103xC, STM32F103xD, STM32F103xE Contents 2.3.29 Serial wire JTAG debug port (SWJ-DP) . . . . . . . . . . . . . . . . . . . . . . . . . 24 2.3.30 Embedded Trace Macrocell™ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3 Pinouts and pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 4 Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 5 Electrical characteristics . . . . . . . . . . . .
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Contents 6 STM32F103xC, STM32F103xD, STM32F103xE 5.3.20 DAC electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 5.3.21 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 6.1 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 6.2 Thermal characteristics . . . . . . . . . .
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STM32F103xC, STM32F103xD, STM32F103xE List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. Table 43. Device summary . . .
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List of tables Table 44. Table 45. Table 46. Table 47. Table 48. Table 49. Table 50. Table 51. Table 52. Table 53. Table 54. Table 55. Table 56. Table 57. Table 58. Table 59. Table 60. Table 61. Table 62. Table 63. Table 64. Table 65. Table 66. Table 67. Table 68. Table 69. Table 70. Table 71. Table 72. Table 73. Table 74. 6/136 STM32F103xC, STM32F103xD, STM32F103xE Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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STM32F103xC, STM32F103xD, STM32F103xE List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Figure 38.
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List of figures Figure 39. Figure 40. Figure 41. Figure 42. Figure 43. Figure 44. Figure 45. Figure 46. Figure 47. Figure 48. Figure 49. Figure 50. Figure 51. Figure 52. Figure 53. Figure 54. Figure 55. Figure 56. Figure 57. Figure 58. Figure 59. Figure 60. Figure 61. Figure 62. Figure 63. Figure 64. Figure 65. Figure 66. Figure 67. Figure 68. Figure 69. Figure 70. Figure 71. Figure 72. Figure 73. Figure 74. Figure 75. Figure 76.
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STM32F103xC, STM32F103xD, STM32F103xE 1 Introduction Introduction This datasheet provides the ordering information and mechanical device characteristics of the STM32F103xC, STM32F103xD and STM32F103xE high-density performance line microcontrollers. For more details on the whole STMicroelectronics STM32F103xx family, please refer to Section 2.2: Full compatibility throughout the family. The high-density STM32F103xx datasheet should be read in conjunction with the STM32F10xxx reference manual.
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Description 2 STM32F103xC, STM32F103xD, STM32F103xE Description The STM32F103xC, STM32F103xD and STM32F103xE performance line family incorporates the high-performance ARM® Cortex®-M3 32-bit RISC core operating at a 72 MHz frequency, high-speed embedded memories (Flash memory up to 512 Kbytes and SRAM up to 64 Kbytes), and an extensive range of enhanced I/Os and peripherals connected to two APB buses.
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STM32F103xC, STM32F103xD, STM32F103xE 2.1 Description Device overview The STM32F103xx high-density performance line family offers devices in six different package types: from 64 pins to 144 pins. Depending on the device chosen, different sets of peripherals are included, the description below gives an overview of the complete range of peripherals proposed in this family. Figure 1 shows the general block diagram of the device family. Table 2.
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Description STM32F103xC, STM32F103xD, STM32F103xE Figure 1.STM32F103xC, STM32F103xD and STM32F103xE performance line block diagram Ibus Cortex-M3 CPU Fmax: 48/72 MHz NVIC AHB: Fmax = 48/72 MHz GP DMA2 FSMC PLL Reset & Clock control AHB2 APB2 GPIO port C PD[15:0] GPIO port D PE[15:0] GPIO port E PF[15:0] GPIO port F PG[15:0] GPIO port G TIM1 VREF– VREF+ @VDD XTAL OSC 4-16 MHz RTC Backup reg AWU Backup interface AHB2 APB1 VSS NRST VDDA VSSA OSC_IN OSC_OUT VBAT =1.8 V to 3.
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STM32F103xC, STM32F103xD, STM32F103xE Description Figure 2.Clock tree FLITFCLK to Flash programming interface USB Prescaler /1, 1.5 USBCLK to USB interface 48 MHz I2S3CLK Peripheral clock enable 8 MHz HSI RC I2S2CLK to I2S2 Peripheral clock enable Peripheral clock enable HSI SDIOCLK FSMCCLK Peripheral clock enable 72 MHz max /2 PLLSRC to I2S3 /8 SW PLLMUL HSI ..., x16 x2, x3, x4 PLL SYSCLK AHB Prescaler 72 MHz /1, 2..
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Description 2.2 STM32F103xC, STM32F103xD, STM32F103xE Full compatibility throughout the family The STM32F103xx is a complete family whose members are fully pin-to-pin, software and feature compatible. In the reference manual, the STM32F103x4 and STM32F103x6 are identified as low-density devices, the STM32F103x8 and STM32F103xB are referred to as medium-density devices and the STM32F103xC, STM32F103xD and STM32F103xE are referred to as high-density devices.
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STM32F103xC, STM32F103xD, STM32F103xE 2.3 Overview 2.3.1 ARM® Cortex®-M3 core with embedded Flash and SRAM Description The ARM Cortex®-M3 processor is the latest generation of ARM processors for embedded systems. It has been developed to provide a low-cost platform that meets the needs of MCU implementation, with a reduced pin count and low-power consumption, while delivering outstanding computational performance and an advanced system response to interrupts.
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Description 2.3.6 STM32F103xC, STM32F103xD, STM32F103xE LCD parallel interface The FSMC can be configured to interface seamlessly with most graphic LCD controllers. It supports the Intel 8080 and Motorola 6800 modes, and is flexible enough to adapt to specific LCD interfaces. This LCD parallel interface capability makes it easy to build costeffective graphic applications using LCD modules with embedded controllers or highperformance solutions using external controllers with dedicated acceleration. 2.3.
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STM32F103xC, STM32F103xD, STM32F103xE 2.3.10 Description Boot modes At startup, boot pins are used to select one of three boot options: ● Boot from user Flash: you have an option to boot from any of two memory banks. By default, boot from Flash memory bank 1 is selected. You can choose to boot from Flash memory bank 2 by setting a bit in the option bytes. ● Boot from system memory ● Boot from embedded SRAM The boot loader is located in system memory.
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Description 2.3.14 STM32F103xC, STM32F103xD, STM32F103xE Low-power modes The STM32F103xC, STM32F103xD and STM32F103xE performance line supports three low-power modes to achieve the best compromise between low power consumption, short startup time and available wakeup sources: ● Sleep mode In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can wake up the CPU when an interrupt/event occurs.
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STM32F103xC, STM32F103xD, STM32F103xE Description periodic interrupt. It is clocked by a 32.768 kHz external crystal, resonator or oscillator, the internal low power RC oscillator or the high-speed external clock divided by 128. The internal low-speed RC has a typical frequency of 40 kHz. The RTC can be calibrated using an external 512 Hz output to compensate for any natural quartz deviation.
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Description STM32F103xC, STM32F103xD, STM32F103xE Advanced-control timers (TIM1 and TIM8) The two advanced-control timers (TIM1 and TIM8) can each be seen as a three-phase PWM multiplexed on 6 channels. They have complementary PWM outputs with programmable inserted dead-times. They can also be seen as a complete general-purpose timer.
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STM32F103xC, STM32F103xD, STM32F103xE Description the main clock. It has an early warning interrupt capability and the counter can be frozen in debug mode. SysTick timer This timer is dedicated to real-time operating systems, but could also be used as a standard down counter. It features: 2.3.18 ● A 24-bit down counter ● Autoreload capability ● Maskable system interrupt generation when the counter reaches 0.
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Description STM32F103xC, STM32F103xD, STM32F103xE mode, the master clock can be output to the external DAC/CODEC at 256 times the sampling frequency. 2.3.22 SDIO An SD/SDIO/MMC host interface is available, that supports MultiMediaCard System Specification Version 4.2 in three different databus modes: 1-bit (default), 4-bit and 8-bit. The interface allows data transfer at up to 48 MHz in 8-bit mode, and is compliant with SD Memory Card Specifications Version 2.0. The SDIO Card Specification Version 2.
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STM32F103xC, STM32F103xD, STM32F103xE Description The ADC can be served by the DMA controller. An analog watchdog feature allows very precise monitoring of the converted voltage of one, some or all selected channels. An interrupt is generated when the converted voltage is outside the programmed thresholds.
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Description 2.3.28 STM32F103xC, STM32F103xD, STM32F103xE Temperature sensor The temperature sensor has to generate a voltage that varies linearly with temperature. The conversion range is between 2 V < VDDA < 3.6 V. The temperature sensor is internally connected to the ADC1_IN16 input channel which is used to convert the sensor output voltage into a digital value. 2.3.
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STM32F103xC, STM32F103xD, STM32F103xE 3 Pinouts and pin descriptions Pinouts and pin descriptions Figure 3.
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Pinouts and pin descriptions STM32F103xC, STM32F103xD, STM32F103xE Figure 4.
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STM32F103xC, STM32F103xD, STM32F103xE Pinouts and pin descriptions 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 VDD_3 VSS_3 PE1 PE0 PB9 PB8 BOOT0 PB7 PB6 PB5 PB4 PB3 PG15 VDD_11 VSS_11 PG14 PG13 PG12 PG11 PG10 PG9 PD7 PD6 VDD_10 VSS_10 PD5 PD4 PD3 PD2 PD1 PD0 PC12 PC11 PC10 PA15 PA14 Figure 5.
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Pinouts and pin descriptions STM32F103xC, STM32F103xD, STM32F103xE 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 VDD_3 VSS_3 PE1 PE0 PB9 PB8 BOOT0 PB7 PB6 PB5 PB4 PB3 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 PC12 PC11 PC10 PA15 PA14 Figure 6.
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STM32F103xC, STM32F103xD, STM32F103xE Pinouts and pin descriptions VDD_3 VSS_3 PB9 PB8 BOOT0 PB7 PB6 PB5 PB4 PB3 PD2 PC12 PC11 PC10 PA15 PA14 Figure 7.
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Pinouts and pin descriptions STM32F103xC, STM32F103xD, STM32F103xE Figure 8.
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STM32F103xC, STM32F103xD, STM32F103xE Pinouts and pin descriptions Alternate functions(4) WLCSP64 LQFP64 LQFP100 LQFP144 Default LFBGA100 Main function(3) (after reset) LFBGA144 Type(1) Pins I / O Level(2) Table 5.
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Pinouts and pin descriptions STM32F103xC, STM32F103xD, STM32F103xE - - 20 31 VREF- S VREF- - 21 32 VREF+ S VREF+ M1 K1 G8 13 22 33 VDDA S VDDA K1 H1 L1 J2 J1 F7 (8) LQFP144 LQFP100 Main function(3) (after reset) LQFP64 Type(1) Alternate functions(4) WLCSP64 LFBGA100 LFBGA144 Pins I / O Level(2) Table 5.
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STM32F103xC, STM32F103xD, STM32F103xE Pinouts and pin descriptions Alternate functions(4) LFBGA100 WLCSP64 LQFP64 LQFP100 LQFP144 Main function(3) (after reset) LFBGA144 Type(1) Pins I / O Level(2) Table 5.
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Pinouts and pin descriptions STM32F103xC, STM32F103xD, STM32F103xE Alternate functions(4) LQFP100 J9 H9 - - 57 79 PD10 I/O FT PD10 FSMC_D15 USART3_CK H9 G9 - - 58 80 PD11 I/O FT PD11 FSMC_A16 USART3_CTS L10 K10 - - 59 81 PD12 I/O FT PD12 FSMC_A17 TIM4_CH1 / USART3_RTS K10 J10 - - 60 82 PD13 I/O FT PD13 FSMC_A18 TIM4_CH2 G8 - - - - 83 VSS_8 S VSS_8 F8 - - - - 84 VDD_8 S VDD_8 K11 H10 - - 61 85 PD14 I/O FT PD14 FSMC_D0 TIM4_CH3 K12 G10 - -
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STM32F103xC, STM32F103xD, STM32F103xE Pinouts and pin descriptions A12 A10 D4 46 72 105 C11 F8 - - Pin name PA13 Type(1) LQFP144 LQFP100 LQFP64 WLCSP64 LFBGA100 LFBGA144 Pins I / O Level(2) Table 5.
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Pinouts and pin descriptions STM32F103xC, STM32F103xD, STM32F103xE Alternate functions(4) Default Remap I/O FT JTDO SPI3_SCK / I2S3_CK/ PB3/TRACESWO TIM2_CH2 / SPI1_SCK A6 A6 B4 56 90 134 PB4 I/O FT NJTRST SPI3_MISO PB4 / TIM3_CH1 SPI1_MISO B6 C5 A5 57 91 135 PB5 I/O PB5 I2C1_SMBA/ SPI3_MOSI I2S3_SD TIM3_CH2 / SPI1_MOSI C6 B5 B5 58 92 136 PB6 I/O FT PB6 I2C1_SCL(9)/ TIM4_CH1(9) USART1_TX LQFP144 PB3 LQFP100 A7 A4 55 89 133 LQFP64 A7 WLCSP64 LFBGA100 Main function(3) (afte
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STM32F103xC, STM32F103xD, STM32F103xE Pinouts and pin descriptions Table 6.
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Pinouts and pin descriptions STM32F103xC, STM32F103xD, STM32F103xE Table 6.
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STM32F103xC, STM32F103xD, STM32F103xE 4 Memory mapping Memory mapping The memory map is shown in Figure 9. Figure 9.
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Electrical characteristics STM32F103xC, STM32F103xD, STM32F103xE 5 Electrical characteristics 5.1 Parameter conditions Unless otherwise specified, all voltages are referenced to VSS. 5.1.
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STM32F103xC, STM32F103xD, STM32F103xE 5.1.6 Electrical characteristics Power supply scheme Figure 12.Power supply scheme 6"!4 "ACKUP CIRCUITRY /3# + 24# 7AKE UP LOGIC "ACKUP REGISTERS /54 '0 ) /S ). ,EVEL SHIFTER 0O WER SWI TCH 6 )/ ,OGIC +ERNEL LOGIC #05 $IGITAL -EMORIES 6$$ 6$$ 2EGULATOR § N& § & 633 6$$ 6$$! 62%& N& & N& & 62%& 62%& !$# $!# !NALOG 2#S 0,, 633! AI Caution: In Figure 12, the 4.
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Electrical characteristics 5.2 STM32F103xC, STM32F103xD, STM32F103xE Absolute maximum ratings Stresses above the absolute maximum ratings listed in Table 7: Voltage characteristics, Table 8: Current characteristics, and Table 9: Thermal characteristics may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Table 7.
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STM32F103xC, STM32F103xD, STM32F103xE Electrical characteristics Table 9.Thermal characteristics Symbol TSTG TJ Ratings Storage temperature range Maximum junction temperature 5.3 Operating conditions 5.3.1 General operating conditions Value Unit –65 to +150 °C 150 °C Table 10.
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Electrical characteristics 5.3.2 STM32F103xC, STM32F103xD, STM32F103xE Operating conditions at power-up / power-down The parameters given in Table 11 are derived from tests performed under the ambient temperature condition summarized in Table 10. Table 11.Operating conditions at power-up / power-down Symbol Parameter tVDD 5.3.
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STM32F103xC, STM32F103xD, STM32F103xE 5.3.4 Electrical characteristics Embedded reference voltage The parameters given in Table 13 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 10. Table 13.Embedded internal reference voltage Symbol VREFINT Parameter Internal reference voltage Conditions Min Typ –40 °C < TA < +105 °C 1.16 1.20 1.26 V –40 °C < TA < +85 °C 1.16 1.20 1.24 V - 5.1 17.
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Electrical characteristics STM32F103xC, STM32F103xD, STM32F103xE Table 14.Maximum current consumption in Run mode, code with data processing running from Flash Max(1) Symbol Parameter Conditions Unit TA = 85 °C TA = 105 °C 72 MHz 69 70 48 MHz 50 50.5 36 MHz 39 39.5 24 MHz 27 28 16 MHz 20 20.5 8 MHz 11 11.5 72 MHz 37 37.5 48 MHz 28 28.5 External clock(2), all 36 MHz peripherals disabled 24 MHz 22 22.5 16.5 17 16 MHz 12.
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STM32F103xC, STM32F103xD, STM32F103xE Electrical characteristics Figure 14.Typical current consumption in Run mode versus frequency (at 3.6 V) code with data processing running from RAM, peripherals enabled 70 8 MHz 16 MHz 24 MHz 36 MHz 48 MHz 72 MHz 60 Consumption (mA) 50 40 30 20 10 0 -45 25 70 85 105 Temperature (°C) Figure 15.Typical current consumption in Run mode versus frequency (at 3.
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Electrical characteristics STM32F103xC, STM32F103xD, STM32F103xE Table 16.Maximum current consumption in Sleep mode, code running from Flash or RAM Max(1) Symbol Parameter Conditions External clock(2), all peripherals enabled IDD Supply current in Sleep mode fHCLK Unit TA = 85 °C TA = 105 °C 72 MHz 45 46 48 MHz 31 32 36 MHz 24 25 24 MHz 17 17.5 16 MHz 12.5 13 8 MHz 8 8 72 MHz 8.5 9 48 MHz 7 7.5 36 MHz 6 6.5 24 MHz 5 5.5 16 MHz 4.
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STM32F103xC, STM32F103xD, STM32F103xE Electrical characteristics Table 17.Typical and maximum current consumptions in Stop and Standby modes Typ(1) Symbol Parameter Conditions VDD/VBAT VDD/VBAT VDD/VBAT TA = TA = = 2.0 V = 2.4 V = 3.
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Electrical characteristics STM32F103xC, STM32F103xD, STM32F103xE Figure 17.Typical current consumption in Stop mode with regulator in run mode versus temperature at different VDD values 700 600 Consumption (µA) 500 400 300 200 2.4V 2.7V 3.0V 3.3V 3.
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STM32F103xC, STM32F103xD, STM32F103xE Electrical characteristics Figure 18.Typical current consumption in Stop mode with regulator in low-power mode versus temperature at different VDD values 700 600 Consumption (µA) 500 400 300 200 2.4V 2.7V 3.0V 3.3V 3.
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Electrical characteristics STM32F103xC, STM32F103xD, STM32F103xE Figure 19.Typical current consumption in Standby mode versus temperature at different VDD values 4.5 4 Consumption (µA) 3.5 3 2.5 2 1.5 2.4V 2.7V 3.0V 3.3V 3.6V 1 0.
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STM32F103xC, STM32F103xD, STM32F103xE Electrical characteristics Typical current consumption The MCU is placed under the following conditions: ● All I/O pins are in input mode with a static value at VDD or VSS (no load). ● All peripherals are disabled except if it is explicitly mentioned. ● The Flash access time is adjusted to fHCLK frequency (0 wait state from 0 to 24 MHz, 1 wait state from 24 to 48 MHZ and 2 wait states above).
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Electrical characteristics STM32F103xC, STM32F103xD, STM32F103xE Table 19.Typical current consumption in Sleep mode, code running from Flash or RAM Typ(1) Symbol Parameter Conditions 29.5 6.4 48 MHz 20 4.6 36 MHz 15.1 3.6 24 MHz 10.4 2.6 16 MHz 7.2 2 8 MHz 3.9 1.3 4 MHz 2.6 1.2 2 MHz 1.85 1.15 1 MHz 1.5 1.1 500 kHz 1.3 1.05 125 kHz 1.2 1.05 64 MHz 25.6 5.1 48 MHz 19.4 4 36 MHz 14.
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STM32F103xC, STM32F103xD, STM32F103xE Electrical characteristics On-chip peripheral current consumption The current consumption of the on-chip peripherals is given in Table 20.
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Electrical characteristics STM32F103xC, STM32F103xD, STM32F103xE Table 20.Peripheral current consumption(1) (continued) Peripheral APB2 Typical consumption at 25 °C GPIOA 0.55 GPIOB 0.72 GPIOC 0.72 GPIOD 0.55 GPIOE 1 GPIOF 0.72 GPIOG 1 ADC1(2) 1.9 ADC2 1.7 TIM1 1.8 SPI1 0.4 TIM8 1.7 USART1 0.9 ADC3 1.7 Unit mA 1. fHCLK = 72 MHz, fAPB1 = fHCLK/2, fAPB2 = fHCLK, default prescaler value for each peripheral. 2.
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STM32F103xC, STM32F103xD, STM32F103xE Electrical characteristics Low-speed external user clock generated from an external source The characteristics given in Table 22 result from tests performed using an low-speed external clock source, and under ambient temperature and supply voltage conditions summarized in Table 10. Table 22.Low-speed external user clock characteristics Symbol Parameter Conditions Min Typ Max Unit - 32.768 1000 kHz 0.
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Electrical characteristics STM32F103xC, STM32F103xD, STM32F103xE Figure 21.
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STM32F103xC, STM32F103xD, STM32F103xE Electrical characteristics High-speed external clock generated from a crystal/ceramic resonator The high-speed external (HSE) clock can be supplied with a 4 to 16 MHz crystal/ceramic resonator oscillator. All the information given in this paragraph are based on characterization results obtained with typical external components specified in Table 23.
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Electrical characteristics STM32F103xC, STM32F103xD, STM32F103xE Low-speed external clock generated from a crystal/ceramic resonator The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal/ceramic resonator oscillator. All the information given in this paragraph are based on characterization results obtained with typical external components specified in Table 24.
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STM32F103xC, STM32F103xD, STM32F103xE Electrical characteristics Figure 23.Typical application with a 32.768 kHz crystal Resonator with integrated capacitors CL1 fLSE OSC32_IN 32.768 kH z resonator Bias controlled gain RF STM32F103xx OSC32_OU T CL2 ai14146 5.3.7 Internal clock source characteristics The parameters given in Table 25 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 10. High-speed internal (HSI) RC oscillator Table 25.
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Electrical characteristics STM32F103xC, STM32F103xD, STM32F103xE Low-speed internal (LSI) RC oscillator Table 26.LSI oscillator characteristics (1) Symbol fLSI(2) Parameter Frequency Min Typ Max Unit 30 40 60 kHz tsu(LSI)(3) LSI oscillator startup time - - 85 µs IDD(LSI)(3) LSI oscillator power consumption - 0.65 1.2 µA 1. VDD = 3 V, TA = –40 to 105 °C unless otherwise specified. 2. Based on characterization, not tested in production. 3.
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STM32F103xC, STM32F103xD, STM32F103xE 5.3.8 Electrical characteristics PLL characteristics The parameters given in Table 28 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 10. Table 28.PLL characteristics Value Symbol Parameter Unit Min Typ Max(1) PLL input clock(2) 1 8.
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Electrical characteristics STM32F103xC, STM32F103xD, STM32F103xE Table 30.Flash memory endurance and data retention Value Symbol NEND tRET Parameter Endurance Data retention Conditions TA = –40 to +85 °C (6 suffix versions) TA = –40 to +105 °C (7 suffix versions) 10 1 kcycle(2) at TA = 85 °C 30 1 kcycle (2) 10 kcycles at TA = 105 °C 10 (2) 20 at TA = 55 °C 1. Based on characterization not tested in production. 2. Cycling performed over the whole temperature range.
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STM32F103xC, STM32F103xD, STM32F103xE 5.3.10 Electrical characteristics FSMC characteristics Asynchronous waveforms and timings Figure 24 through Figure 27 represent asynchronous waveforms and Table 31 through Table 34 provide the corresponding timings. The results shown in these tables are obtained with the following FSMC configuration: ● AddressSetupTime = 0 ● AddressHoldTime = 1 ● DataSetupTime = 1 Figure 24.Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms TW .% &3-#?.% T V ./%?.
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Electrical characteristics STM32F103xC, STM32F103xD, STM32F103xE Table 31.Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings(1) Symbol Parameter Min tw(NE) FSMC_NE low time tv(NOE_NE) FSMC_NEx low to FSMC_NOE low tw(NOE) FSMC_NOE low time th(NE_NOE) FSMC_NOE high to FSMC_NE high hold time tv(A_NE) FSMC_NEx low to FSMC_A valid th(A_NOE) Address hold time after FSMC_NOE high tv(BL_NE) 5tHCLK – 1.5 Max Unit 5tHCLK + 2 ns 0.5 1.5 ns 5tHCLK – 1.5 5tHCLK + 1.5 ns –1.
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STM32F103xC, STM32F103xD, STM32F103xE Electrical characteristics Table 32.Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings(1)(2) Symbol Parameter Min Max Unit tw(NE) FSMC_NE low time 3tHCLK – 1 3tHCLK + 2 ns tv(NWE_NE) FSMC_NEx low to FSMC_NWE low tHCLK – 0.5 tHCLK + 1.
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Electrical characteristics STM32F103xC, STM32F103xD, STM32F103xE Table 33.Asynchronous multiplexed PSRAM/NOR read timings(1)(2) Symbol Parameter Min Max Unit tw(NE) FSMC_NE low time 7tHCLK – 2 7tHCLK + 2 ns tv(NOE_NE) FSMC_NEx low to FSMC_NOE low 3tHCLK – 0.5 3tHCLK + 1.
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STM32F103xC, STM32F103xD, STM32F103xE Electrical characteristics Table 34.
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Electrical characteristics STM32F103xC, STM32F103xD, STM32F103xE Figure 28.Synchronous multiplexed NOR/PSRAM read timings "53452. TW #,+ TW #,+ &3-#?#,+ $ATA LATENCY TD #,+, .%X, T D #,+, .%X( &3-#?.%X TD #,+, .!$6, TD #,+, .!$6( &3-#?.!$6 TD #,+, !)6 TD #,+, !6 &3-#?!; = TD #,+, ./%( TD #,+, ./%, &3-#?./% TD #,+, !$)6 TSU !$6 #,+( TD #,+, !$6 !$; = &3-#?!$; = TH #,+( !$6 TSU !$6 #,+( $ TSU .7!)46 #,+( TH #,+( !$6 $ $ TH #,+( .7!)46 &3-#?.
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STM32F103xC, STM32F103xD, STM32F103xE Electrical characteristics Table 35.Synchronous multiplexed NOR/PSRAM read timings(1)(2) Symbol Parameter Min Max Unit 27.7 - ns tw(CLK) FSMC_CLK period td(CLKL-NExL) FSMC_CLK low to FSMC_NEx low (x = 0...2) - 1.5 ns td(CLKL-NExH) FSMC_CLK low to FSMC_NEx high (x = 0...2) 2 - ns td(CLKL-NADVL) FSMC_CLK low to FSMC_NADV low - 4 ns td(CLKL-NADVH) FSMC_CLK low to FSMC_NADV high 5 - ns td(CLKL-AV) FSMC_CLK low to FSMC_Ax valid (x = 16...
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Electrical characteristics STM32F103xC, STM32F103xD, STM32F103xE Figure 29.Synchronous multiplexed PSRAM write timings "53452. TW #,+ TW #,+ &3-#?#,+ $ATA LATENCY TD #,+, .%X, TD #,+, .%X( &3-#?.%X TD #,+, .!$6, TD #,+, .!$6( &3-#?.!$6 TD #,+, !6 TD #,+, !)6 &3-#?!; = TD #,+, .7%, TD #,+, .7%( &3-#?.7% TD #,+, !$)6 TD #,+, $ATA TD #,+, $ATA TD #,+, !$6 !$; = &3-#?!$; = $ $ &3-#?.7!)4 7!)4#&' B 7!)40/, B TSU .7!)46 #,+( TH #,+( .7!)46 TD #,+, .",( &3-#?.
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STM32F103xC, STM32F103xD, STM32F103xE Electrical characteristics Table 36.Synchronous multiplexed PSRAM write timings(1)(2) Symbol Parameter Min Max Unit 27.7 - ns tw(CLK) FSMC_CLK period td(CLKL-NExL) FSMC_CLK low to FSMC_Nex low (x = 0...2) - 2 ns td(CLKL-NExH) FSMC_CLK low to FSMC_NEx high (x = 0...2) 2 - ns td(CLKL-NADVL) FSMC_CLK low to FSMC_NADV low - 4 ns td(CLKL-NADVH) FSMC_CLK low to FSMC_NADV high 5 - ns td(CLKL-AV) FSMC_CLK low to FSMC_Ax valid (x = 16...
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Electrical characteristics STM32F103xC, STM32F103xD, STM32F103xE Figure 30.Synchronous non-multiplexed NOR/PSRAM read timings "53452. TW #,+ TW #,+ &3-#?#,+ TD #,+, .%X, TD #,+, .%X( $ATA LATENCY &3-#?.%X TD #,+, .!$6, TD #,+, .!$6( &3-#?.!$6 TD #,+, !)6 TD #,+, !6 &3-#?!; = TD #,+, ./%, TD #,+, ./%( &3-#?./% TSU $6 #,+( TH #,+( $6 TSU $6 #,+( $ &3-#?$; = TSU .7!)46 #,+( TH #,+( $6 $ $ TH #,+( .7!)46 &3-#?.7!)4 7!)4#&' B 7!)40/, B TSU .7!)46 #,+( T H #,+( .
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STM32F103xC, STM32F103xD, STM32F103xE Electrical characteristics Figure 31.Synchronous non-multiplexed PSRAM write timings TW #,+ "53452. TW #,+ &3-#?#,+ TD #,+, .%X, TD #,+, .%X( $ATA LATENCY &3-#?.%X TD #,+, .!$6, TD #,+, .!$6( &3-#?.!$6 TD #,+, !6 TD #,+, !)6 &3-#?!; = TD #,+, .7%, TD #,+, .7%( &3-#?.7% TD #,+, $ATA &3-#?$; = TD #,+, $ATA $ $ &3-#?.7!)4 7!)4#&' B 7!)40/, B TSU .7!)46 #,+( TD #,+, .",( TH #,+( .7!)46 &3-#?.", AI H Table 38.
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Electrical characteristics STM32F103xC, STM32F103xD, STM32F103xE PC Card/CompactFlash controller waveforms and timings Figure 32 through Figure 37 represent synchronous waveforms and Table 39 provides the corresponding timings. The results shown in this table are obtained with the following FSMC configuration: ● COM.FSMC_SetupTime = 0x04; ● COM.FSMC_WaitSetupTime = 0x07; ● COM.FSMC_HoldSetupTime = 0x04; ● COM.FSMC_HiZSetupTime = 0x00; ● ATT.FSMC_SetupTime = 0x04; ● ATT.
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STM32F103xC, STM32F103xD, STM32F103xE Electrical characteristics Figure 33.
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Electrical characteristics STM32F103xC, STM32F103xD, STM32F103xE Figure 34.PC Card/CompactFlash controller waveforms for attribute memory read access FSMC_NCE4_1 tv(NCE4_1-A) FSMC_NCE4_2 th(NCE4_1-AI) High FSMC_A[10:0] FSMC_NIOWR FSMC_NIORD td(NREG-NCE4_1) th(NCE4_1-NREG) FSMC_NREG FSMC_NWE td(NCE4_1-NOE) tw(NOE) td(NOE-NCE4_1) FSMC_NOE tsu(D-NOE) th(NOE-D) FSMC_D[15:0](1) ai14897b 1. Only data bits 0...7 are read (bits 8...15 are disregarded).
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STM32F103xC, STM32F103xD, STM32F103xE Electrical characteristics Figure 35.PC Card/CompactFlash controller waveforms for attribute memory write access FSMC_NCE4_1 FSMC_NCE4_2 High tv(NCE4_1-A) th(NCE4_1-AI) FSMC_A[10:0] FSMC_NIOWR FSMC_NIORD td(NREG-NCE4_1) th(NCE4_1-NREG) FSMC_NREG td(NCE4_1-NWE) tw(NWE) FSMC_NWE td(NWE-NCE4_1) FSMC_NOE tv(NWE-D) FSMC_D[7:0](1) ai14898b 1. Only data bits 0...7 are driven (bits 8...15 remains HiZ). Figure 36.
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Electrical characteristics STM32F103xC, STM32F103xD, STM32F103xE Figure 37.PC Card/CompactFlash controller waveforms for I/O space write access &3-#?.#% ? &3-#?.#% ? TV .#%X ! TH .#% ? !) &3-#?!; = &3-#?.2%' &3-#?.7% &3-#?./% &3-#?.)/2$ TD .#% ? .)/72 TW .)/72 &3-#?.)/72 !44X(): TV .)/72 $ TH .)/72 $ &3-#?$; = AI B Table 39.
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STM32F103xC, STM32F103xD, STM32F103xE Electrical characteristics Table 39.
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Electrical characteristics STM32F103xC, STM32F103xD, STM32F103xE Figure 38.NAND controller waveforms for read access FSMC_NCEx Low ALE (FSMC_A17) CLE (FSMC_A16) FSMC_NWE td(ALE-NOE) th(NOE-ALE) FSMC_NOE (NRE) tsu(D-NOE) th(NOE-D) FSMC_D[15:0] ai14901b Figure 39.NAND controller waveforms for write access FSMC_NCEx Low ALE (FSMC_A17) CLE (FSMC_A16) td(ALE-NWE) th(NWE-ALE) FSMC_NWE FSMC_NOE (NRE) tv(NWE-D) th(NWE-D) FSMC_D[15:0] ai14902b Figure 40.
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STM32F103xC, STM32F103xD, STM32F103xE Electrical characteristics Figure 41.NAND controller waveforms for common memory write access FSMC_NCEx Low ALE (FSMC_A17) CLE (FSMC_A16) td(ALE-NOE) tw(NWE) th(NOE-ALE) FSMC_NWE FSMC_NOE td(D-NWE) tv(NWE-D) th(NWE-D) FSMC_D[15:0] ai14913b Table 40.
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Electrical characteristics 5.3.11 STM32F103xC, STM32F103xD, STM32F103xE EMC characteristics Susceptibility tests are performed on a sample basis during device characterization. Functional EMS (electromagnetic susceptibility) While a simple application is executed on the device (toggling 2 LEDs through I/O ports). the device is stressed by two electromagnetic events until a failure occurs.
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STM32F103xC, STM32F103xD, STM32F103xE Electrical characteristics Prequalification trials Most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1 second. To complete these trials, ESD stress can be applied directly on the device, over the range of specification values.
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Electrical characteristics STM32F103xC, STM32F103xD, STM32F103xE Static latch-up Two complementary static tests are required on six parts to assess the latch-up performance: ● A supply overvoltage is applied to each power supply pin ● A current injection is applied to each input, output and configurable I/O pin These tests are compliant with EIA/JESD 78A IC latch-up standard. Table 44.Electrical sensitivities Symbol LU 5.3.
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STM32F103xC, STM32F103xD, STM32F103xE 5.3.14 Electrical characteristics I/O port characteristics General input/output characteristics Unless otherwise specified, the parameters given in Table 46 are derived from tests performed under the conditions summarized in Table 10. All I/Os are CMOS and TTL compliant. Table 46.I/O static characteristics Symbol VIL VIH Vhys Ilkg Parameter Min Typ Max Unit Standard IO input low level voltage –0.3 - 0.28*(VDD-2 V)+0.
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Electrical characteristics STM32F103xC, STM32F103xD, STM32F103xE Figure 42.Standard I/O input characteristics - CMOS port 6)( 6), 6 6 $$ T 6 )( 3 STAND #-/ 7)(MIN 7),MAX RD #-/3 STANDA 6 6 $$ REQUIREMENT ), 6 ), 6 ## )NPUT RANGE NOT GUARANTEED 6 6 )( $$ IREMEN ARD REQU 6$$ 6 AI B Figure 43.
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STM32F103xC, STM32F103xD, STM32F103xE Electrical characteristics Figure 45.
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Electrical characteristics STM32F103xC, STM32F103xD, STM32F103xE Table 47.Output voltage characteristics (continued) Symbol VOL(1)(4) VOH (2)(4) VOL(1)(4) VOH (2)(4) Parameter Output low level voltage for an I/O pin when 8 pins are sunk at same time Output high level voltage for an I/O pin when 8 pins are sourced at same time Conditions IIO = +20 mA 2.7 V < VDD < 3.
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STM32F103xC, STM32F103xD, STM32F103xE Electrical characteristics Input/output AC characteristics The definition and values of input/output AC characteristics are given in Figure 46 and Table 48, respectively. Unless otherwise specified, the parameters given in Table 48 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 10. Table 48.
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Electrical characteristics STM32F103xC, STM32F103xD, STM32F103xE Figure 46.I/O AC characteristics definition 90% 10% 50% 50% 90% 10% EXT ERNAL OUTPUT ON 50pF tr(I O)out tr(I O)out T Maximum frequency is achieved if (tr + tf) 2/3)T and if the duty cycle is (45-55%) when loaded by 50pF ai14131 5.3.15 NRST pin characteristics The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up resistor, RPU (see Table 46).
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STM32F103xC, STM32F103xD, STM32F103xE 5.3.16 Electrical characteristics TIM timer characteristics The parameters given in Table 50 are guaranteed by design. Refer to Section 5.3.14: I/O port characteristics for details on the input/output alternate function characteristics (output compare, input capture, external clock, PWM output). Table 50.TIMx(1) characteristics Symbol tres(TIM) fEXT ResTIM tCOUNTER Parameter Conditions Min Max Unit 1 - tTIMxCLK 13.
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Electrical characteristics 5.3.17 STM32F103xC, STM32F103xD, STM32F103xE Communications interfaces I2C interface characteristics Unless otherwise specified, the parameters given in Table 51 are derived from tests performed under ambient temperature, fPCLK1 frequency and VDD supply voltage conditions summarized in Table 10.
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STM32F103xC, STM32F103xD, STM32F103xE Electrical characteristics Figure 48.I2C bus AC waveforms and measurement circuit VDD VDD 4 .7 k 4 .7 k STM32F103xx 100 SDA I2C bus 100 SCL S TART REPEATED S TART S TART tsu(STA) SDA tf(SDA) tr(SDA) th(STA) SCL tw(SCLH) tsu(SDA) th(SDA) tw(SCLL) tr(SCL) S TOP tf(SCL) tw(STO:STA) tsu(STO) ai14149c 1. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD. Table 52.SCL frequency (fPCLK1= 36 MHz.,VDD = 3.
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Electrical characteristics STM32F103xC, STM32F103xD, STM32F103xE I2S - SPI characteristics Unless otherwise specified, the parameters given in Table 53 for SPI or in Table 54 for I2S are derived from tests performed under ambient temperature, fPCLKx frequency and VDD supply voltage conditions summarized in Table 10. Refer to Section 5.3.14: I/O port characteristics for more details on the input/output alternate function characteristics (NSS, SCK, MOSI, MISO for SPI and WS, CK, SD for I2S). Table 53.
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STM32F103xC, STM32F103xD, STM32F103xE Electrical characteristics Figure 49.SPI timing diagram - slave mode and CPHA = 0 NSS input tc(SCK) th(NSS) SCK Input tSU(NSS) CPHA= 0 CPOL=0 tw(SCKH) tw(SCKL) CPHA= 0 CPOL=1 tv(SO) ta(SO) MISO OUT P UT tr(SCK) tf(SCK) th(SO) MS B O UT BI T6 OUT tdis(SO) LSB OUT tsu(SI) MOSI I NPUT B I T1 IN M SB IN LSB IN th(SI) ai14134c Figure 50.
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Electrical characteristics STM32F103xC, STM32F103xD, STM32F103xE Figure 51.SPI timing diagram - master mode(1) (IGH .33 INPUT 3#+ /UTPUT #0(! #0/, 3#+ /UTPUT TC 3#+ #0(! #0/, #0(! #0/, #0(! #0/, TSU -) -)3/ ).0 54 TW 3#+( TW 3#+, -3 "). TR 3#+ TF 3#+ ") 4 ). ,3" ). TH -) -/3) /54054 - 3" /54 TV -/ " ) 4 /54 ,3" /54 TH -/ AI 6 1. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD.
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STM32F103xC, STM32F103xD, STM32F103xE Electrical characteristics Table 54.I2S characteristics Symbol DuCy(SCK) Parameter Conditions Min Max Unit 30 70 % 1.522 1.525 Slave mode 0 6.
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Electrical characteristics STM32F103xC, STM32F103xD, STM32F103xE Figure 52.I2S slave timing diagram (Philips protocol)(1) CK Input tc(CK) CPOL = 0 CPOL = 1 tw(CKH) th(WS) tw(CKL) WS input tv(SD_ST) tsu(WS) SDtransmit LSB transmit(2) MSB transmit Bitn transmit tsu(SD_SR) LSB receive(2) SDreceive th(SD_ST) LSB transmit th(SD_SR) MSB receive Bitn receive LSB receive ai14881b 1. Measurement points are done at CMOS levels: 0.3 × VDD and 0.7 × VDD. 2.
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STM32F103xC, STM32F103xD, STM32F103xE Electrical characteristics SD/SDIO MMC card host interface (SDIO) characteristics Unless otherwise specified, the parameters given in Table 55 are derived from tests performed under ambient temperature, fPCLKx frequency and VDD supply voltage conditions summarized in Table 10. Refer to Section 5.3.14: I/O port characteristics for more details on the input/output alternate function characteristics (D[7:0], CMD, CK). Figure 54.
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Electrical characteristics STM32F103xC, STM32F103xD, STM32F103xE Table 55.
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STM32F103xC, STM32F103xD, STM32F103xE Electrical characteristics Table 57.USB DC electrical characteristics Symbol Parameter Conditions Min.(1) Max.(1) Unit 3.0(3) 3.6 V V Input levels VDD (4) USB operating voltage(2) I(USBDP, USBDM) 0.2 VCM(4) Differential common mode range Includes VDI range 0.8 2.5 VSE(4) Single ended receiver threshold 1.3 2.0 VDI Differential input sensitivity Output levels VOL Static output level low RL of 1.5 kΩ to 3.
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Electrical characteristics 5.3.19 STM32F103xC, STM32F103xD, STM32F103xE 12-bit ADC characteristics Unless otherwise specified, the parameters given in Table 59 are preliminary values derived from tests performed under ambient temperature, fPCLK2 frequency and VDDA supply voltage conditions summarized in Table 10. Note: It is recommended to perform a calibration after each power-up. Table 59.ADC characteristics Symbol Parameter Conditions Min Typ Max Unit VDDA Power supply 2.4 - 3.
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STM32F103xC, STM32F103xD, STM32F103xE Electrical characteristics Equation 1: RAIN max formula TS - – R ADC R AIN < --------------------------------------------------------------N+2 f ADC × C ADC × ln ( 2 ) The formula above (Equation 1) is used to determine the maximum external impedance allowed for an error below 1/4 of LSB. Here N = 12 (from 12-bit resolution). Table 60.RAIN max for fADC = 14 MHz(1) Ts (cycles) tS (µs) RAIN max (kΩ) 1.5 0.11 0.4 7.5 0.54 5.9 13.5 0.96 11.4 28.5 2.04 25.
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Electrical characteristics STM32F103xC, STM32F103xD, STM32F103xE Table 62.ADC accuracy(1) (2)(3) Symbol Parameter ET Test conditions Total unadjusted error EO Offset error EG Gain error ED Differential linearity error EL Integral linearity error fPCLK2 = 56 MHz, fADC = 14 MHz, RAIN < 10 kΩ, VDDA = 2.4 V to 3.6 V Measurements made after ADC calibration Typ Max(4) ±2 ±5 ±1.5 ±2.5 ±1.5 ±3 ±1 ±2 ±1.5 ±3 Unit LSB 1. ADC DC accuracy values are measured after internal calibration. 2.
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STM32F103xC, STM32F103xD, STM32F103xE Electrical characteristics Figure 58.Typical connection diagram using the ADC VDD RAIN(1) VAIN VT 0.6 V AINx Cparasitic VT 0.6 V IL±1 µA STM32F103xx Sample and hold ADC converter RADC(1) 12-bit converter CADC(1) ai14150c 1. Refer to Table 59 for the values of RAIN, RADC and CADC. 2. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the pad capacitance (roughly 7 pF).
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Electrical characteristics STM32F103xC, STM32F103xD, STM32F103xE Figure 60.Power supply and reference decoupling (VREF+ connected to VDDA) STM32F103xx VREF+/VDDA (See note 1) 1 µF // 10 nF VREF–/VSSA (See note 1) ai14389 1. VREF+ and VREF– inputs are available only on 100-pin packages.
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STM32F103xC, STM32F103xD, STM32F103xE 5.3.20 Electrical characteristics DAC electrical specifications Table 63.DAC characteristics Symbol Parameter Min Typ Max Unit Comments VDDA Analog supply voltage 2.4 - 3.6 V VREF+ Reference supply voltage 2.4 - 3.6 V VSSA Ground 0 - 0 V RLOAD(1) Resistive load with buffer ON 5 RO(1) Impedance output with buffer OFF - - 15 When the buffer is OFF, the Minimum resistive load between DAC_OUT kΩ and VSS to have a 1% accuracy is 1.
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Electrical characteristics STM32F103xC, STM32F103xD, STM32F103xE Table 63.DAC characteristics (continued) Symbol Parameter Min Typ Max Unit Comments - - ±10 mV Given for the DAC in 12-bit configuration Offset error (difference between measured value at Code (0x800) and the ideal value = VREF+/2) - - ±3 LSB Given for the DAC in 10-bit at VREF+ = 3.6 V - - ±12 LSB Given for the DAC in 12-bit at VREF+ = 3.6 V Gain error - - ±0.
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STM32F103xC, STM32F103xD, STM32F103xE 5.3.21 Electrical characteristics Temperature sensor characteristics Table 64.TS characteristics Symbol Parameter Min Typ Max Unit - ±1 ±2 °C TL VSENSE linearity with temperature Avg_Slope Average slope 4.0 4.3 4.6 mV/°C V25 Voltage at 25 °C 1.34 1.43 1.52 V tSTART(1) Startup time 4 - 10 µs TS_temp(2)(1) ADC sampling time when reading the temperature - - 17.1 µs 1. Guaranteed by design, not tested in production. 2.
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Package characteristics STM32F103xC, STM32F103xD, STM32F103xE 6 Package characteristics 6.1 Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. Figure 62.BGA pad footprint $PAD $SM -3 6 Table 65.Recommended PCB design rules (0.80/0.
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STM32F103xC, STM32F103xD, STM32F103xE Package characteristics Figure 63.LFBGA144 – 144-ball low profile fine pitch ball grid array, 10 x 10 mm, 0.8 mm pitch, package outline C Seating plane A2 ddd A4 C A A3 A1 B D D1 e A F M F E1 E e Øb (144 balls) Ball A1 Ø eee M C A Ø fff M B C X3_ME 1. Drawing is not to scale. Table 66.LFBGA144 – 144-ball low profile fine pitch ball grid array, 10 x 10 mm, 0.8 mm pitch, package data inches(1) millimeters Symbol Min Typ A A1 Max Typ Min 1.70 0.
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Package characteristics STM32F103xC, STM32F103xD, STM32F103xE Figure 64.LFBGA100 - 10 x 10 mm low profile fine pitch ball grid array package outline 1. Drawing is not to scale. Table 67.LFBGA100 - 10 x 10 mm low profile fine pitch ball grid array package mechanical data inches(1) millimeters Symbol Min Typ A A1 Max Min 1.700 0.270 Max 0.0669 0.0106 A2 1.085 0.0427 A3 0.30 0.0118 A4 0.80 0.0315 b 0.45 0.50 0.55 0.0177 0.0197 0.0217 D 9.85 10.00 10.15 0.3878 0.3937 0.
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STM32F103xC, STM32F103xD, STM32F103xE Package characteristics Figure 65.WLCSP, 64-ball 4.466 × 4.395 mm, 0.500 mm pitch, wafer-level chip-scale package outline e1 A1 ball corner e D A1 ball corner e A H Detail A B C D e1 E E F Notch G L F H aaa Marking area A2 L G Wafer back side 8 A 7 6 5 4 Ball side 3 2 1 Side view Ball eee A1 b Seating plane (see note 2) Detail A rotated 90 ˚ CR_ME 1. Drawing is not to scale. 2.
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Package characteristics STM32F103xC, STM32F103xD, STM32F103xE Figure 66.BGA pad footprint $PAD $SM -3 6 Table 69.Recommended PCB design rules (0.5mm pitch BGA) Dimension Recommended values Dpad ∅ = 300 µm (circular) - 250 µm recommended Dsm ∅ = 340 µm min (for 300 µm diameter pad) PCD pad size Cu - Ni (2-6 µm) - Au (0.
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STM32F103xC, STM32F103xD, STM32F103xE Package characteristics Figure 67.LQFP144, 20 x 20 mm, 144-pin low-profile quad flat package outline C ! ! ! 3%!4).' 0,!.% # MM CCC # ! '!5'% 0,!.% $ + , $ , $ % % % B 0). )$%.4)&)#!4)/. E !?-%?6 1. Drawing is not to scale. Dimensions are in millimeter. Table 70.
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Package characteristics STM32F103xC, STM32F103xD, STM32F103xE Table 70.LQFP144, 20 x 20 mm, 144-pin low-profile quad flat package mechanical data inches(1) millimeters Symbol Min Typ Max Min Typ Max E3 - 17.500 - - 0.6890 - e - 0.500 - - 0.0197 - L 0.450 0.600 0.750 0.0177 0.0236 0.0295 L1 - 1.000 - - 0.0394 - k 0° 3.5° 7° 0° 3.5° 7° ccc - - 0.08 - - 0.0031 1. Values in inches are converted from mm and rounded to 4 decimal digits. Figure 68.
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STM32F103xC, STM32F103xD, STM32F103xE Package characteristics Device marking for LQFP144 The following figure shows the device marking for the LQFP144 package. Figure 69.LQFP144 marking example (package top view) 2SWLRQDO JDWH PDUN 5HYLVLRQ FRGH 3URGXFW LGHQWLILFDWLRQ ; 670 ) =(7 'DWH FRGH < :: 3LQ LGHQWLILHU 06Y 9 1.
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Package characteristics STM32F103xC, STM32F103xD, STM32F103xE Figure 70.LFP100 – 14 x 14 mm 100 pin low-profile quad flat package outline MM C ! ! ! 3%!4).' 0,!.% # '!5'% 0,!.% $ , $ ! + CCC # , $ 0). )$%.4)&)#!4)/. E 1. Drawing is not to scale.
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STM32F103xC, STM32F103xD, STM32F103xE Package characteristics Table 71.LQPF100 – 14 x 14 mm 100-pin low-profile quad flat package mechanical data inches(1) millimeters Symbol Min Typ Max Min Typ Max A - - 1.600 - - 0.0630 A1 0.050 - 0.150 0.0020 - 0.0059 A2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.170 0.220 0.270 0.0067 0.0087 0.0106 c 0.090 - 0.200 0.0035 - 0.0079 D 15.800 16.000 16.200 0.6220 0.6299 0.6378 D1 13.800 14.000 14.200 0.5433 0.5512 0.
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Package characteristics STM32F103xC, STM32F103xD, STM32F103xE Device marking for LQFP100 The following figure shows the device marking for the LQFP100 package. Figure 72.LQFP100 marking example (package top view) 2SWLRQDO JDWH PDUN 3URGXFW LGHQWLILFDWLRQ ^dDϯϮ&ϭϬϯ 5HYLVLRQ FRGH sϴdϲ y 'DWH FRGH z tt 3LQ LGHQWLILHU 06Y 9 1.
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STM32F103xC, STM32F103xD, STM32F103xE Package characteristics Figure 73.LFP64 – 10 x 10 mm 64 pin low-profile quad flat package outline PP *$8*( 3/$1( F $ $ $ 6($7,1* 3/$1( & $ FFF & ' ' ' . / / ( ( ( E 3,1 ,'(17,),&$7,21 H :B0(B9 1. Drawing is not in scale. Table 72.LQFP64 – 10 x 10 mm 64 pin low-profile quad flat package mechanical data inches(1) millimeters Symbol Min Typ Max Min Typ Max A - - 1.600 - - 0.0630 A1 0.
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Package characteristics STM32F103xC, STM32F103xD, STM32F103xE Table 72.LQFP64 – 10 x 10 mm 64 pin low-profile quad flat package mechanical data inches(1) millimeters Symbol Min Typ Max Min Typ Max θ 0° 3.5° 7° 0° 3.5° 7° L 0.450 0.600 0.750 0.0177 0.0236 0.0295 L1 - 1.000 - - 0.0394 - ccc - - 0.080 - - 0.0031 1. Values in inches are converted from mm and rounded to 4 decimal digits. Figure 74.
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STM32F103xC, STM32F103xD, STM32F103xE Package characteristics Device marking for LQFP64 The following figure shows the device marking for the LQFP64 package. Figure 75.LQFP64 marking example (package top view) 5HYLVLRQ FRGH 3URGXFW LGHQWLILFDWLRQ ^dDϯϮ&ϭϬϯ Z dϲ z tt 3LQ LGHQWLILHU 'DWH FRGH 06Y 9 1.
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Package characteristics 6.2 STM32F103xC, STM32F103xD, STM32F103xE Thermal characteristics The maximum chip junction temperature (TJmax) must never exceed the values given in Table 10: General operating conditions on page 43.
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STM32F103xC, STM32F103xD, STM32F103xE 6.2.2 Package characteristics Selecting the product temperature range When ordering the microcontroller, the temperature range is specified in the ordering information scheme shown in Table 74: Ordering information scheme. Each temperature range suffix corresponds to a specific guaranteed ambient temperature at maximum dissipation and, to a specific maximum junction temperature.
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Package characteristics STM32F103xC, STM32F103xD, STM32F103xE Using the values obtained in Table 73 TJmax is calculated as follows: – For LQFP100, 46 °C/W TJmax = 115 °C + (46 °C/W × 134 mW) = 115 °C + 6.2 °C = 121.2 °C This is within the range of the suffix 7 version parts (–40 < TJ < 125 °C). In this case, parts must be ordered at least with the temperature range suffix 7 (see Table 74: Ordering information scheme). Figure 76.LQFP100 PD max vs.
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STM32F103xC, STM32F103xD, STM32F103xE 7 Part numbering Part numbering Table 74.
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Revision history 8 STM32F103xC, STM32F103xD, STM32F103xE Revision history Table 75.Document revision history Date Revision 07-Apr-2008 1 Initial release. 2 Document status promoted from Target Specification to Preliminary Data. Section 1: Introduction and Section 2.2: Full compatibility throughout the family modified. Small text changes. Note 2 added in Table 2: STM32F103xC, STM32F103xD and STM32F103xE features and peripheral counts on page 11.
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STM32F103xC, STM32F103xD, STM32F103xE Revision history Table 75.Document revision history Date 21-Jul-2008 Revision Changes 3 Document status promoted from Preliminary Data to full datasheet. FSMC (flexible static memory controller) on page 22 modified. Number of complementary channels corrected in Figure 1: STM32F103xF, STM32F103xD and STM32F103xGSTM32F103xF and STM32F103xG performance line block diagram.
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Revision history STM32F103xC, STM32F103xD, STM32F103xE Table 75.Document revision history Date 12-Dec-2008 132/136 Revision Changes 4 Timers specified on page 1 (motor control capability mentioned). Section 2.2: Full compatibility throughout the family updated. Table 6: High-density timer feature comparison added. General-purpose timers (TIMx) and Advanced-control timers (TIM1 and TIM8) on page 27 updated.
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STM32F103xC, STM32F103xD, STM32F103xE Revision history Table 75.Document revision history Date 30-Mar-2009 Revision Changes 5 I/O information clarified on page 1. Figure 4: STM32F103xC and STM32F103xE performance line BGA100 ballout corrected. I/O information clarified on page 1.
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Revision history STM32F103xC, STM32F103xD, STM32F103xE Table 75.Document revision history Date 21-Jul-2009 24-Sep-2009 134/136 Revision Changes 6 Figure 1: STM32F103xC, STM32F103xD and STM32F103xE performance line block diagram updated. Note 5 updated and Note 4 added in Table 5: High-density STM32F103xx pin definitions. VRERINT and TCoeff added to Table 13: Embedded internal reference voltage. Table 16: Maximum current consumption in Sleep mode, code running from Flash or RAM modified.
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STM32F103xC, STM32F103xD, STM32F103xE Revision history Table 75.Document revision history Date 19-Apr-2011 30-Sept-2014 23-Feb-2015 Revision Changes 8 Updated package choice for 103Rx in Table 2 Updated footnotes below Table 7: Voltage characteristics on page 42 and Table 8: Current characteristics on page 42 Updated tw min in Table 21: High-speed external user clock characteristics on page 56 Updated startup time in Table 24: LSE oscillator characteristics (fLSE = 32.
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STM32F103xC, STM32F103xD, STM32F103xE IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement.