Datasheet

STM32F103x8, STM32F103xB Electrical characteristics
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SPI interface characteristics
Unless otherwise specified, the parameters given in Ta ble 4 0 are derived from tests
performed under the ambient temperature, f
PCLKx
frequency and V
DD
supply voltage
conditions summarized in Ta bl e 8 .
Refer to Section 5.3.12: I/O port characteristics for more details on the input/output alternate
function characteristics (NSS, SCK, MOSI, MISO).
Table 40. SPI characteristics
(1)
1. Remapped SPI1 characteristics to be determined.
Symbol Parameter Conditions Min Max Unit
f
SCK
1/t
c(SCK)
SPI clock frequency
Master mode 0 18
MHz
Slave mode 0 18
t
r(SCK)
t
f(SCK)
SPI clock rise and fall
time
Capacitive load: C = 30 pF 8
ns
t
su(NSS)
(2)
2. Based on characterization, not tested in production.
NSS setup time Slave mode 4 t
PCLK
t
h(NSS)
(2)
NSS hold time Slave mode 73
t
w(SCKH)
(2)
t
w(SCKL)
(2)
SCK high and low time
Master mode, f
PCLK
= 36 MHz,
presc = 4
50 60
t
su(MI)
(2)
Data input setup time
Master mode
SPI1 1
SPI2 5
t
su(SI)
(2)
Data input setup time
Slave mode
1
t
h(MI)
(2)
Data input hold time
Master mode
SPI1 1
SPI2 5
t
h(SI)
(2)
Data input hold time
Slave mode
3
t
a(SO)
(2)(3)
3. Min time is for the minimum time to drive the output and the max time is for the maximum time to validate
the data.
Data output access
time
Slave mode, f
PCLK
= 36 MHz,
presc = 4
055
Slave mode, f
PCLK
= 24 MHz 0 4 t
PCLK
t
dis(SO)
(2)(4)
4. Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put
the data in Hi-Z
Data output disable
time
Slave mode 10
t
v(SO)
(2)(1)
Data output valid time Slave mode (after enable edge) 25
t
v(MO)
(2)(1)
Data output valid time Master mode (after enable edge) 3
t
h(SO)
(2)
Data output hold time
Slave mode (after enable edge) 25
t
h(MO)
(2)
Master mode (after enable edge) 4