Datasheet

Description STM32F103x8, STM32F103xB
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Serial wire JTAG debug port (SWJ-DP)
The ARM SWJ-DP Interface is embedded. and is a combined JTAG and serial wire debug
port that enables either a serial wire debug or a JTAG probe to be connected to the target.
The JTAG TMS and TCK pins are shared with SWDIO and SWCLK, respectively, and a
specific sequence on the TMS pin is used to switch between JTAG-DP and SW-DP.
Figure 1. STM32F103xx performance line block diagram
1. T
A
= –40 °C to +105 °C (junction temperature up to 125 °C).
2. AF = alternate function on I/O port pin.
USBDP/CANTX
PA[15:0]
EXTI
WWDG
12bit ADC1
16AF
JTDI
JTCK/SWCLK
JTMS/SWDIO
JNTRST
JTDO
NRST
V
DD
= 2 to 3.6V
80AF
PB[15:0]
PC[15:0]
AHB2
MOSI,MISO,SCK,NSS
SRAM
2x(8x16bit)
WAKEUP
GPIOA
GPIOB
GPIOC
F
max
: 72 M Hz
V
SS
SCL,SDA
I2C2
V
REF+
GP DMA
TIM2
TIM3
XTAL OSC
4-16 MHz
XTAL 32 kHz
OSC_IN
OSC_OUT
OSC32_OUT
OSC32_IN
PLL &
APB1 : F
max
=24 / 36 MHz
PCLK1
HCLK
CLOCK
MANAGT
PCLK2
as AF
as AF
Flash 128 KB
VOLT. REG.
3.3V TO 1.8V
POWER
Backu p i nterf ace
as AF
TIM 4
BusM atrix
64 bit
Interfac e
20 KB
RTC
RC 8 MHz
Cortex-M3 CPU
Ibus
Dbus
pbu s
obl
flash
SRAM 512B
Trace
Controlle r
USART1
USART2
SPI2
bxCAN
7 channels
Backup
reg
4 Channels
TIM1
3 co mpl. Chann els
SCL,SDA,SMBA L
I2C1
as AF
RX,TX, CTS, RTS,
USART3
Temp sensor
V
REF-
PD[15:0]
GPIOD
PE[15:0]
GPIOE
AHB:F
max
=48/72 MHz
Brk i npu t
4 Channels
4 Channels
4 Channels
FCLK
RC 40 kHz
Stand by
IWDG
@VBAT
POR / PDR
SUPPLY
@VDDA
VDDA
VSSA
@VDDA
V
BAT
RX,TX, CTS, RTS,
Smart Card as AF
RX,TX, CTS, RTS,
CK, SmartCard as AF
APB2 : F
max
=48 / 72 MHz
NVIC
SPI1
MOSI,MISO,
SCK,NSS as AF
12bi t ADC2
IF
IFIF
interface
@VDDA
SUPERVISION
PVD
Rst
Int
@VDD
AHB2
APB2
APB 1
AWU
TAMPER-RTC
@VDD
USB 2.0 FS
USBDM/CANRX
Syst em
ai14390b
TRACECLK
TRACED[0:3]
as AS
SW/JTAG
TPIU
Trace/trig
CK, SmartCard as AF