Datasheet

ManualsBrandsST ManualsEmbedded Processors & ControllersMicrocontroller 32bit 128KB LQFP

September 2008 Rev 9 1/84

STM32F103x8

STM32F103xB

Medium-density performance line ARM-based 32-bit MCU with 64 or

128 KB Flash, USB, CAN, 7 timers, 2 ADCs, 9 communication interfaces

Features

■ Core: ARM 32-bit Cortex™-M3 CPU

– 72 MHz maximum frequency,

1.25 DMIPS/MHz (Dhrystone 2.1)

performance at 0 wait state memory

access

– Single-cycle multiplication and hardware

division

■ Memories

– 64 or 128 Kbytes of Flash memory

– 20 Kbytes of SRAM

■ Clock, reset and supply management

– 2.0 to 3.6 V application supply and I/Os

– POR, PDR, and programmable voltage

detector (PVD)

– 4-to-16 MHz crystal oscillator

– Internal 8 MHz factory-trimmed RC

– Internal 40 kHz RC

– PLL for CPU clock

– 32 kHz oscillator for RTC with calibration

■ Low power

– Sleep, Stop and Standby modes

–V

BAT

supply for RTC and backup registers

■ 2 x 12-bit, 1 µs A/D converters (up to 16

channels)

– Conversion range: 0 to 3.6 V

– Dual-sample and hold capability

– Temperature sensor

■ DMA

– 7-channel DMA controller

– Peripherals supported: timers, ADC, SPIs,

Cs and USARTs

■ Up to 80 fast I/O ports

– 26/37/51/80 I/Os, all mappable on 16

external interrupt vectors, all 5 V-tolerant

except for analog inputs

■ Debug mode

– Serial wire debug (SWD) & JTAG interfaces

■ 7 timers

– Three 16-bit timers, each with up to 4

IC/OC/PWM or pulse counter

– 16-bit, 6-channel advanced control timer:

up to 6 channels for PWM output, dead-

time generation and emergency stop

– 2 watchdog timers (Independent and

Window)

– SysTick timer: a 24-bit downcounter

■ Up to 9 communication interfaces

– Up to 2 x I

C interfaces (SMBus/PMBus)

– Up to 3 USARTs (ISO 7816 interface, LIN,

IrDA capability, modem control)

– Up to 2 SPIs (18 Mbit/s)

– CAN interface (2.0B Active)

– USB 2.0 full-speed interface

■ CRC calculation unit, 96-bit unique ID

■ Packages are ECOPACK

Table 1. Device summary

Reference Part number

STM32F103x8

STM32F103C8, STM32F103R8

STM32F103V8, STM32F103T8

STM32F103xB

STM32F103RB STM32F103VB,

STM32F103CB

LQFP64

10 x 10 mm

LQFP100

14 x 14 mm

LQFP48

7 x 7 mm

BGA100

10 x 10 mm

VFQFPN36

6 × 6 mm

www.st.com

Summary of content (84 pages)

PAGE 1
STM32F103x8 STM32F103xB Medium-density performance line ARM-based 32-bit MCU with 64 or 128 KB Flash, USB, CAN, 7 timers, 2 ADCs, 9 communication interfaces Features ■ Core: ARM 32-bit Cortex™-M3 CPU – 72 MHz maximum frequency, 1.25 DMIPS/MHz (Dhrystone 2.1) performance at 0 wait state memory access – Single-cycle multiplication and hardware division ■ Memories – 64 or 128 Kbytes of Flash memory – 20 Kbytes of SRAM ■ Clock, reset and supply management – 2.0 to 3.
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Contents STM32F103x8, STM32F103xB Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.1 Device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.2 Full compatibility throughout the family . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.3 Overview . . .
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STM32F103x8, STM32F103xB 6 Contents 5.3.13 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 5.3.14 TIM timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 5.3.15 Communications interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 5.3.16 CAN (controller area network) interface . . . . . . . . . . . . . . . . . . . . . . . . . 62 5.3.17 12-bit ADC characteristics . . . . . .
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List of tables STM32F103x8, STM32F103xB List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. Table 43. Table 44. 4/84 Device summary .
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STM32F103x8, STM32F103xB Table 45. Table 46. Table 47. Table 48. Table 49. Table 50. Table 51. Table 52. Table 53. Table 54. Table 55. List of tables RAIN max for fADC = 14 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 ADC accuracy - limited test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 ADC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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List of figures STM32F103x8, STM32F103xB List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Figure 38. Figure 39. Figure 40. Figure 41. Figure 42.
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STM32F103x8, STM32F103xB 1 Introduction Introduction This datasheet provides the ordering information and mechanical device characteristics of the STM32F103x8 and STM32F103xB medium-density performance line microcontrollers. For more details on the whole STMicroelectronics STM32F103xx family, please refer to Section 2.2: Full compatibility throughout the family. The medium-density STM32F103xx datasheet should be read in conjunction with the low-, medium- and high-density STM32F10xxx reference manual.
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Description 2.1 STM32F103x8, STM32F103xB Device overview Table 2.
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STM32F103x8, STM32F103xB 2.2 Description Full compatibility throughout the family The STM32F103xx is a complete family whose members are fully pin-to-pin, software and feature compatible. In the reference manual, the STM32F103x4 and STM32F103x6 are identified as low-density devices, the STM32F103x8 and STM32F103xB are referred to as medium-density devices, and the STM32F103xC, STM32F103xD and STM32F103xE are referred to as high-density devices.
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Description 2.3 STM32F103x8, STM32F103xB Overview ARM® CortexTM-M3 core with embedded Flash and SRAM The ARM Cortex™-M3 processor is the latest generation of ARM processors for embedded systems. It has been developed to provide a low-cost platform that meets the needs of MCU implementation, with a reduced pin count and low-power consumption, while delivering outstanding computational performance and an advanced system response to interrupts.
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STM32F103x8, STM32F103xB Description External interrupt/event controller (EXTI) The external interrupt/event controller consists of 19 edge detector lines used to generate interrupt/event requests. Each line can be independently configured to select the trigger event (rising edge, falling edge, both) and can be masked independently. A pending register maintains the status of the interrupt requests. The EXTI can detect an external line with a pulse width shorter than the Internal APB2 clock period.
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Description STM32F103x8, STM32F103xB than the VPVD threshold. The interrupt service routine can then generate a warning message and/or put the MCU into a safe state. The PVD is enabled by software. Refer to Table 10: Embedded reset and power control block characteristics for the values of VPOR/PDR and VPVD. Voltage regulator The regulator has three operation modes: main (MR), low power (LPR) and power down.
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STM32F103x8, STM32F103xB Description Each channel is connected to dedicated hardware DMA requests, with support for software trigger on each channel. Configuration is made by software and transfer sizes between source and destination are independent. The DMA can be used with the main peripherals: SPI, I2C, USART, general-purpose and advanced-control timers TIMx and ADC.
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Description STM32F103x8, STM32F103xB The general-purpose timers can work together with the advanced-control timer via the Timer Link feature for synchronization or event chaining. Their counter can be frozen in debug mode. Any of the general-purpose timers can be used to generate PWM outputs. They all have independent DMA request generation. These timers are capable of handling quadrature (incremental) encoder signals and the digital outputs from 1 to 3 hall-effect sensors.
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STM32F103x8, STM32F103xB Description Controller area network (CAN) The CAN is compliant with specifications 2.0A and B (active) with a bit rate up to 1 Mbit/s. It can receive and transmit standard frames with 11-bit identifiers as well as extended frames with 29-bit identifiers. It has three transmit mailboxes, two receive FIFOs with 3 stages and 14 scalable filter banks. Universal serial bus (USB) The STM32F103xx performance line embeds a USB device peripheral compatible with the USB full-speed 12 Mbs.
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Description STM32F103x8, STM32F103xB Serial wire JTAG debug port (SWJ-DP) The ARM SWJ-DP Interface is embedded. and is a combined JTAG and serial wire debug port that enables either a serial wire debug or a JTAG probe to be connected to the target. The JTAG TMS and TCK pins are shared with SWDIO and SWCLK, respectively, and a specific sequence on the TMS pin is used to switch between JTAG-DP and SW-DP.
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STM32F103x8, STM32F103xB Figure 2. Description Clock tree 8 MHz HSI RC HSI USB Prescaler /1, 1.5 /2 USBCLK to USB interface 48 MHz 72 MHz max PLLSRC /8 SW PLLMUL HSI ..., x16 x2, x3, x4 PLL SYSCLK AHB Prescaler 72 MHz /1, 2..
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Pin descriptions STM32F103x8, STM32F103xB 3 Pin descriptions Figure 3.
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STM32F103x8, STM32F103xB STM32F103xx performance line LQFP100 pinout 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 VDD_3 VSS_3 PE1 PE0 PB9 PB8 BOOT0 PB7 PB6 PB5 PB4 PB3 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 PC12 PC11 PC10 PA15 PA14 Figure 4.
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Pin descriptions STM32F103xx performance line LQFP64 pinout VDD_3 VSS_3 PB9 PB8 BOOT0 PB7 PB6 PB5 PB4 PB3 PD2 PC12 PC11 PC10 PA15 PA14 Figure 5.
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STM32F103x8, STM32F103xB PB7 PB6 PB5 PB4 PB3 PA15 PA14 36 BOOT0 VSS_3 STM32F103xx Performance Line VFQFPN36 pinout 35 34 33 32 31 30 29 28 VDD_3 1 27 VDD_2 OSC_IN/PD0 2 26 VSS_2 OSC_OUT/PD1 3 25 PA13 NRST 4 24 PA12 23 PA11 VSSA 5 VDDA 6 22 PA10 PA0-WKUP 7 21 PA9 PA1 8 20 PA8 PA2 9 10 11 12 13 14 15 PA4 PA5 PA6 PA7 PB0 QFN36 PA3 19 18 VDD_1 VSS_1 17 PB2 16 PB1 Figure 7.
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Pin descriptions Medium-density STM32F103xx pin definitions Alternate functions LQFP64 LQFP100 VFQFPN36 Default LQFP48 Main function(3) (after reset) BGA100 Type(1) Pins I / O Level(2) Table 4.
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STM32F103x8, STM32F103xB Medium-density STM32F103xx pin definitions (continued) Alternate functions LQFP48 LQFP64 LQFP100 VFQFPN36 Main function(3) (after reset) BGA100 Type(1) Pins I / O Level(2) Table 4.
PAGE 24
Pin descriptions Medium-density STM32F103xx pin definitions (continued) LQFP48 LQFP64 LQFP100 VFQFPN36 F7 24 32 50 19 Pin name VDD_1 Type(1) BGA100 Pins I / O Level(2) Table 4.
PAGE 25
STM32F103x8, STM32F103xB Medium-density STM32F103xx pin definitions (continued) Pin name Type(1) VFQFPN36 LQFP100 LQFP64 LQFP48 BGA100 Pins I / O Level(2) Table 4.
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Pin descriptions Medium-density STM32F103xx pin definitions (continued) Alternate functions VFQFPN36 I2C1_SDA / CANTX LQFP100 Remap LQFP64 Default LQFP48 Main function(3) (after reset) BGA100 Type(1) Pins I / O Level(2) Table 4. STM32F103x8, STM32F103xB A4 46 62 96 - PB9 I/O FT PB9 TIM4_CH4(6) D4 - - 97 - PE0 I/O FT PE0 TIM4_ETR C4 - - 98 - PE1 I/O FT PE1 E5 47 63 99 36 VSS_3 S VSS_3 F5 48 64 100 1 VDD_3 S VDD_3 Pin name 1.
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STM32F103x8, STM32F103xB 4 Memory mapping Memory mapping The memory map is shown in Figure 8. Figure 8.
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Electrical characteristics 5 Electrical characteristics 5.1 Test conditions STM32F103x8, STM32F103xB Unless otherwise specified, all voltages are referenced to VSS. 5.1.1 Minimum and maximum values Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at TA = 25 °C and TA = TAmax (given by the selected temperature range).
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STM32F103x8, STM32F103xB Figure 9. Electrical characteristics Pin loading conditions Figure 10. Pin input voltage STM32F103xx pin STM32F103xx pin C = 50 pF VIN ai14141 5.1.6 ai14142 Power supply scheme Figure 11. Power supply scheme VBAT Backup circuitry (OSC32K,RTC, Wake-up logic Backup registers) OUT GP I/Os IN Level shifter Po wer swi tch 1.8-3.6V IO Logic Kernel logic (CPU, Digital & Memories) VDD VDD 1/2/3/4/5 5 × 100 nF + 1 × 4.
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Electrical characteristics 5.1.7 STM32F103x8, STM32F103xB Current consumption measurement Figure 12. Current consumption measurement scheme IDD_VBAT VBAT IDD VDD VDDA ai14126 5.2 Absolute maximum ratings Stresses above the absolute maximum ratings listed in Table 5: Voltage characteristics, Table 6: Current characteristics, and Table 7: Thermal characteristics may cause permanent damage to the device.
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STM32F103x8, STM32F103xB Table 6. Electrical characteristics Current characteristics Symbol Ratings Max.
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Electrical characteristics Table 8.
PAGE 33
STM32F103x8, STM32F103xB Table 10. Embedded reset and power control block characteristics Symbol Parameter Programmable voltage detector level selection VPVD VPVDhyst Electrical characteristics (2) VPOR/PDR VPDRhyst (2) Conditions Min Typ Max Unit PLS[2:0]=000 (rising edge) 2.1 2.18 2.26 V PLS[2:0]=000 (falling edge) 2 2.08 2.16 V PLS[2:0]=001 (rising edge) 2.19 2.28 2.37 V PLS[2:0]=001 (falling edge) 2.09 2.18 2.27 V PLS[2:0]=010 (rising edge) 2.28 2.38 2.
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Electrical characteristics 5.3.4 STM32F103x8, STM32F103xB Embedded reference voltage The parameters given in Table 11 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 8. Table 11. Symbol VREFINT Embedded internal reference voltage Parameter Internal reference voltage Conditions Min Typ Max Unit –40 °C < TA < +105 °C 1.16 1.20 1.26 V –40 °C < TA < +85 °C 1.16 1.20 1.24 V 5.1 17.
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STM32F103x8, STM32F103xB Table 12. Electrical characteristics Maximum current consumption in Run mode, code with data processing running from Flash Max(1) Symbol Parameter Conditions fHCLK TA = 105 °C 72 MHz 50 50.3 48 MHz 36.1 36.2 36 MHz 28.6 28.7 24 MHz 19.9 20.1 16 MHz 14.7 14.9 8 MHz 8.6 8.9 72 MHz 32.8 32.9 48 MHz 24.4 24.5 External clock(2), all 36 MHz peripherals disabled 24 MHz 19.8 19.9 13.9 14.2 16 MHz 10.7 11 8 MHz 6.8 7.
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Electrical characteristics STM32F103x8, STM32F103xB Figure 13. Typical current consumption in Run mode versus frequency (at 3.6 V) code with data processing running from RAM, peripherals enabled 45 40 Consumption (mA) 35 30 72 MHz 36 MHz 16 MHz 8 MHz 25 20 15 10 5 0 -40 0 25 70 85 105 Temperature (°C) Figure 14. Typical current consumption in Run mode versus frequency (at 3.
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STM32F103x8, STM32F103xB Table 14. Electrical characteristics Maximum current consumption in Sleep mode, code running from Flash or RAM Max(1) Symbol Parameter Conditions External clock(2), all peripherals enabled IDD Supply current in Sleep mode External clock(2), all peripherals disabled fHCLK Unit TA = 85 °C TA = 105 °C 72 MHz 30 32 48 MHz 20 20.5 36 MHz 15.5 16 24 MHz 11.5 12 16 MHz 8.5 9 8 MHz 5.5 6 72 MHz 7.5 8 48 MHz 6 6.5 36 MHz 5 5.5 24 MHz 4.
PAGE 38
Electrical characteristics Table 15. STM32F103x8, STM32F103xB Typical and maximum current consumptions in Stop and Standby modes Typ(1) Symbol Parameter Conditions Regulator in Run mode, low-speed and high-speed internal RC oscillators and high-speed oscillator OFF (no Supply current in independent watchdog) Stop mode Regulator in Low Power mode, lowspeed and high-speed internal RC oscillators and high-speed oscillator OFF (no independent watchdog) IDD TA = Unit VDD/VBAT VDD/VBAT TA = = 2.4 V = 3.
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STM32F103x8, STM32F103xB Electrical characteristics Figure 16. Current consumption in Stop mode with regulator in Low-power mode versus temperature at VDD = 3.3 V and 3.6 V 300 Consumption (µA) 250 200 3.3 V 150 3.6 V 100 50 0 -40 0 25 70 85 105 Temperature (°C) Figure 17. Typical current consumption in Standby mode versus temperature at VDD = 3.3 V and 3.6 V 4.5 4 Consumption (µA) 3.5 3 2.5 3.3 V 2 3.6 V 1.5 1 0.
PAGE 40
Electrical characteristics STM32F103x8, STM32F103xB Typical current consumption The MCU is placed under the following conditions: ● All I/O pins are in input mode with a static value at VDD or VSS (no load). ● All peripherals are disabled except if it is explicitly mentioned. ● The Flash access time is adjusted to fHCLK frequency (0 wait state from 0 to 24 MHz, 1 wait state from 24 to 48 MHz and 2 wait states above). ● Ambient temperature and VDD supply voltage conditions summarized in Table 8.
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STM32F103x8, STM32F103xB Table 17. Electrical characteristics Typical current consumption in Sleep mode, code with data processing code running from Flash or RAM Typ(1) Symbol Parameter Conditions External clock IDD Supply current in Sleep mode (3) fHCLK All peripherals All peripherals enabled(2) disabled 72 MHz 14.4 5.5 48 MHz 9.9 3.9 36 MHz 7.6 3.1 24 MHz 5.3 2.3 16 MHz 3.8 1.8 8 MHz 2.1 1.2 4 MHz 1.6 1.1 2 MHz 1.3 1 1 MHz 1.11 0.98 500 kHz 1.04 0.96 125 kHz 0.
PAGE 42
Electrical characteristics STM32F103x8, STM32F103xB On-chip peripheral current consumption The current consumption of the on-chip peripherals is given in Table 18.
PAGE 43
STM32F103x8, STM32F103xB 5.3.6 Electrical characteristics External clock source characteristics High-speed external user clock generated from an external source The characteristics given in Table 19 result from tests performed using an high-speed external clock source, and under ambient temperature and supply voltage conditions summarized in Table 8. Table 19.
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Electrical characteristics STM32F103x8, STM32F103xB Figure 18. High-speed external clock source AC timing diagram VHSEH 90% VHSEL 10% tr(HSE) tf(HSE) tW(HSE) tW(HSE) t THSE EXTER NAL CLOCK SOURC E fHSE_ext OSC _IN IL STM32F103xx ai14143 Figure 19.
PAGE 45
STM32F103x8, STM32F103xB Table 21. Symbol HSE 4-16 MHz oscillator characteristics(1) (2) Parameter fOSC_IN Conditions Min Typ Max Unit 4 8 16 MHz Oscillator frequency Feedback resistor RF Recommended load capacitance versus equivalent serial resistance of the crystal (RS)(4) CL1 CL2(3) i2 HSE driving current RS = 30 Ω (5) 200 kΩ 30 pF VDD = 3.
PAGE 46
Electrical characteristics STM32F103x8, STM32F103xB Note: For CL1 and CL2 it is recommended to use high-quality ceramic capacitors in the 5 pF to 15 pF range selected to match the requirements of the crystal or resonator. CL1 and CL2, are usually the same size. The crystal manufacturer typically specifies a load capacitance which is the series combination of CL1 and CL2.
PAGE 47
STM32F103x8, STM32F103xB Electrical characteristics High-speed internal (HSI) RC oscillator HSI oscillator characteristics(1) (2) Table 23. Symbol Parameter fHSI Conditions Min Typ Frequency Max 8 ACCHSI Accuracy of HSI oscillator tsu(HSI) HSI oscillator start up time IDD(HSI) HSI oscillator power consumption Unit MHz TA = –40 to 105 °C ±1 ±3 % TA = –10 to 85 °C ±1 ±2.5 % TA = 0 to 70 °C ±1 ±2.2 % TA = 25 °C ±1 ±2 % 2 µs 100 µA 1 80 1.
PAGE 48
Electrical characteristics Table 25. STM32F103x8, STM32F103xB Low-power mode wakeup timings Symbol Parameter Conditions Typ Unit Wakeup on HSI RC clock 1.8 µs Wakeup from Stop mode (regulator in run mode) HSI RC wakeup time = 2 µs 3.6 Wakeup from Stop mode (regulator in low power mode) HSI RC wakeup time = 2 µs, Regulator wakeup from LP mode time = 5 µs 5.
PAGE 49
STM32F103x8, STM32F103xB Table 27. Symbol IDD Vprog Electrical characteristics Flash memory characteristics (continued) Max(1) Unit Read mode fHCLK = 72 MHz with 2 wait states, VDD = 3.3 V 20 mA Write / Erase modes fHCLK = 72 MHz, VDD = 3.3 V 5 mA Power-down mode / Halt, VDD = 3.0 to 3.6 V 50 µA 3.6 V Parameter Supply current Conditions Programming voltage Min(1) Typ 2 1. Guaranteed by design, not tested in production. Table 28.
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Electrical characteristics Table 29. STM32F103x8, STM32F103xB EMS characteristics Symbol Parameter Level/ Class Conditions VFESD VDD = 3.3 V, TA = +25 °C, Voltage limits to be applied on any I/O pin to fHCLK = 72 MHz induce a functional disturbance conforms to IEC 1000-4-2 2B VEFTB Fast transient voltage burst limits to be applied through 100 pF on VDD and VSS pins to induce a functional disturbance VDD = 3.
PAGE 51
STM32F103x8, STM32F103xB 5.3.11 Electrical characteristics Absolute maximum ratings (electrical sensitivity) Based on three different tests (ESD, LU) using specific measurement methods, the device is stressed in order to determine its performance in terms of electrical sensitivity. Electrostatic discharge (ESD) Electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combination.
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Electrical characteristics 5.3.12 STM32F103x8, STM32F103xB I/O port characteristics General input/output characteristics Unless otherwise specified, the parameters given in Table 33 are derived from tests performed under the conditions summarized in Table 8. All I/Os are CMOS and TTL compliant. Table 33.
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STM32F103x8, STM32F103xB Electrical characteristics Output driving current The GPIOs (general purpose input/outputs) can sink or source up to +/-8 mA, and sink +20 mA (with a relaxed VOL). In the user application, the number of I/O pins which can drive current must be limited to respect the absolute maximum rating specified in Section 5.
PAGE 54
Electrical characteristics STM32F103x8, STM32F103xB Input/output AC characteristics The definition and values of input/output AC characteristics are given in Figure 22 and Table 35, respectively. Unless otherwise specified, the parameters given in Table 35 are derived from tests performed under the ambient temperature and VDD supply voltage conditions summarized in Table 8. Table 35.
PAGE 55
STM32F103x8, STM32F103xB Electrical characteristics Figure 22. I/O AC characteristics definition 90% 10% 50% 50% 90% 10% EXT ERNAL OUTPUT ON 50pF tr(I O)out tr(I O)out T Maximum frequency is achieved if (tr + tf) £ 2/3)T and if the duty cycle is (45-55%) when loaded by 50pF ai14131 5.3.13 NRST pin characteristics The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up resistor, RPU (see Table 33).
PAGE 56
Electrical characteristics STM32F103x8, STM32F103xB Figure 23. Recommended NRST pin protection VDD External reset circuit(1) NRST(2) RPU Internal Reset FILTER 0.1 µF STM32F10xxx ai14132b 2. The reset network protects the device against parasitic resets. 3. The user must ensure that the level on the NRST pin can go below the VIL(NRST) max level specified in Table 36. Otherwise the reset will not be taken into account by the device. 5.3.
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STM32F103x8, STM32F103xB 5.3.15 Electrical characteristics Communications interfaces I2C interface characteristics Unless otherwise specified, the parameters given in Table 38 are derived from tests performed under the ambient temperature, fPCLK1 frequency and VDD supply voltage conditions summarized in Table 8.
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Electrical characteristics STM32F103x8, STM32F103xB Figure 24. I2C bus AC waveforms and measurement circuit VDD VDD 4 .7 kΩ 4 .7 kΩ 100Ω STM32F103xx SDA I2C bus 100Ω SCL S TART REPEATED S TART S TART tsu(STA) SDA tf(SDA) tr(SDA) tw(SCKL) th(STA) SCL tw(SCKH) tsu(SDA) tr(SCK) tsu(STA:STO) S TOP th(SDA) tsu(STO) tf(SCK) ai14149b 1. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD. Table 39. SCL frequency (fPCLK1= 36 MHz.,VDD = 3.3 V)(1)(2) I2C_CCR value fSCL (kHz) RP = 4.
PAGE 59
STM32F103x8, STM32F103xB Electrical characteristics SPI interface characteristics Unless otherwise specified, the parameters given in Table 40 are derived from tests performed under the ambient temperature, fPCLKx frequency and VDD supply voltage conditions summarized in Table 8. Refer to Section 5.3.12: I/O port characteristics for more details on the input/output alternate function characteristics (NSS, SCK, MOSI, MISO). Table 40.
PAGE 60
Electrical characteristics STM32F103x8, STM32F103xB Figure 25. SPI timing diagram - slave mode and CPHA = 0 NSS input tc(SCK) th(NSS) SCK Input tSU(NSS) CPHA= 0 CPOL=0 tw(SCKH) tw(SCKL) CPHA= 0 CPOL=1 tv(SO) ta(SO) MISO OUT P UT tr(SCK) tf(SCK) th(SO) MS B O UT BI T6 OUT tdis(SO) LSB OUT tsu(SI) MOSI I NPUT B I T1 IN M SB IN LSB IN th(SI) ai14134c Figure 26.
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STM32F103x8, STM32F103xB Electrical characteristics Figure 27. SPI timing diagram - master mode(1) High NSS input SCK Input CPHA= 0 CPOL=0 SCK Input tc(SCK) CPHA=1 CPOL=0 CPHA= 0 CPOL=1 CPHA=1 CPOL=1 tsu(MI) MISO INP UT tw(SCKH) tw(SCKL) MS BIN tr(SCK) tf(SCK) BI T6 IN LSB IN th(MI) MOSI OUTUT B I T1 OUT M SB OUT tv(MO) LSB OUT th(MO) ai14136 1. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD. USB characteristics The USB interface is USB-IF certified (Full Speed). Table 41.
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Electrical characteristics Table 42. STM32F103x8, STM32F103xB USB DC electrical characteristics Symbol Parameter Conditions Min.(1) Max.(1) Unit 3.0(3) 3.6 V V Input levels VDD USB operating voltage(2) VDI(4) Differential input sensitivity I(USBDP, USBDM) 0.2 VCM(4) Differential common mode range Includes VDI range 0.8 2.5 VSE(4) Single ended receiver threshold 1.3 2.0 Output levels VOL Static output level low RL of 1.5 kΩ to 3.
PAGE 63
STM32F103x8, STM32F103xB 5.3.17 Electrical characteristics 12-bit ADC characteristics Unless otherwise specified, the parameters given in Table 44 are derived from tests performed under the ambient temperature, fPCLK2 frequency and VDDA supply voltage conditions summarized in Table 8. Note: It is recommended to perform a calibration after each power-up. Table 44. ADC characteristics Symbol Parameter Conditions Min Typ Max Unit VDDA Power supply 2.4 3.
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Electrical characteristics STM32F103x8, STM32F103xB Equation 1: RAIN max formula: TS R AIN < --------------------------------------------------------------- – R ADC N+2 f ADC × C ADC × ln ( 2 ) The formula above (Equation 1) is used to determine the maximum external impedance allowed for an error below 1/4 of LSB. Here N = 12 (from 12-bit resolution). Table 45. RAIN max for fADC = 14 MHz(1) Ts (cycles) tS (µs) RAIN max (kΩ) 1.5 0.11 1.2 7.5 0.54 10 13.5 0.96 19 28.5 2.04 41 41.5 2.
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STM32F103x8, STM32F103xB ADC accuracy(1) (2) (3) Table 47. Symbol ET Electrical characteristics Parameter Test conditions Total unadjusted error EO Offset error EG Gain error ED Differential linearity error EL Integral linearity error fPCLK2 = 56 MHz, fADC = 14 MHz, RAIN < 10 kΩ, VDDA = 2.4 V to 3.6 V Measurements made after ADC calibration Typ Max(4) ±2 ±5 ±1.5 ±2.5 ±1.5 ±3 ±1 ±2 ±1.5 ±3 Unit LSB 1. ADC DC accuracy values are measured after internal calibration. 2.
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Electrical characteristics STM32F103x8, STM32F103xB Figure 30. Typical connection diagram using the ADC VDD RAIN(1) VAIN VT 0.6 V AINx Cparasitic VT 0.6 V IL±1 µA STM32F103xx Sample and hold ADC converter RADC(1) 12-bit converter CADC(1) ai14150c 1. Refer to Table 44 for the values of RAIN, RADC and CADC. 2. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the pad capacitance (roughly 7 pF).
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STM32F103x8, STM32F103xB Electrical characteristics Figure 32. Power supply and reference decoupling (VREF+ connected to VDDA) STM32F103xx VREF+/VDDA (See note 1) 1 µF // 10 nF VREF–/VSSA (See note 1) ai14389 1. VREF+ and VREF– inputs are available only on 100-pin packages. 5.3.18 Temperature sensor characteristics Table 48. TS characteristics Symbol TL(1) Avg_Slope(1) V25(1) tSTART(2) TS_temp(3)(2) Parameter Min VSENSE linearity with temperature Typ Max Unit ±1 ±2 °C Average slope 4.
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Package characteristics 6 Package characteristics 6.1 Package mechanical data STM32F103x8, STM32F103xB In order to meet environmental requirements, ST offers the STM32F103xx in ECOPACK® packages. These packages have a Lead-free second-level interconnect. The category of second-level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label.
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STM32F103x8, STM32F103xB Package characteristics Figure 33. VFQFPN36 6 x 6 mm, 0.5 mm pitch, package outline(1) Figure 34. Recommended footprint (dimensions in mm)(1)(2)(3) Seating plane C ddd C 1.00 4.30 A2 A 27 19 A1 A3 E2 28 18 b 27 19 0.50 4.10 18 28 4.30 4.10 4.80 4.80 e D2 D 36 10 9 1 36 0.75 0.30 10 6.30 ai14870b Pin # 1 ID R = 0.20 1 9 L E ZR_ME 1. Drawing is not to scale. 2. The back-side pad is not internally connected to the VSS or VDD power pads. 3.
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Package characteristics STM32F103x8, STM32F103xB Figure 35. LFBGA100 - low profile fine pitch ball grid array package outline C Seating plane ddd C A2 A4 A3 A1 A D B D1 F e A K J H G F E D C B A F E1 E e 1 2 3 4 5 6 7 8 9 10 A1 corner index area (see note 5) ∅b (100 balls) ∅eee M C A B ∅ fff M C Bottom view ai14396 1. Drawing is not to scale. Table 50. LFBGA100 - low profile fine pitch ball grid array package mechanical data inches(1) mm Dim. Min Typ A A1 Max Min 1.
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STM32F103x8, STM32F103xB Package characteristics Figure 36. Recommended PCB design rules (0.80/0.75 mm pitch BGA) Dpad 0.37 mm 0.52 mm typ. (depends on solder Dsm mask registration tolerance Solder paste 0.
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Package characteristics STM32F103x8, STM32F103xB Figure 38. Recommended footprint(1)(2) Figure 37. LQFP100, 100-pin low-profile quad flat package outline(1) 0.25 mm 0.10 inch GAGE PLANE 75 k 51 D L D1 76 50 0.5 L1 D3 51 75 C 0.3 76 50 16.7 14.3 b E3 E1 E 100 26 1.2 1 100 25 26 Pin 1 1 identification 12.3 25 ccc C 16.7 e A1 ai14906 A2 A SEATING PLANE C 1L_ME 1. Drawing is not to scale. 2. Dimensions are in millimeters. Table 51.
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STM32F103x8, STM32F103xB Package characteristics Figure 39. LQFP64, 64-pin low-profile quad flat package outline(1) Figure 40. Recommended footprint(1)(2) A A2 48 33 A1 0.3 49 E 32 0.5 b E1 12.7 10.3 10.3 e 64 17 1.2 1 16 7.8 D1 c 12.7 L1 D ai14909 L ai14398b 1. Drawing is not to scale. 2. Dimensions are in millimeters. Table 52. LQFP64, 64-pin low-profile quad flat package mechanical data inches(1) mm Dim. Min Typ A Max Min Typ 1.60 A1 0.05 A2 1.35 b 0.17 c 0.
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Package characteristics STM32F103x8, STM32F103xB Figure 41. LQFP48, 48-pin low-profile quad flat package outline(1) Figure 42. Recommended footprint(1)(2) Seating plane C A A2 A1 c b ccc 0.50 0.25 mm Gage plane C 1.20 D 36 0.30 25 37 D1 24 k D3 36 A1 L 25 9.70 0.20 7.30 5.80 L1 7.30 24 37 48 13 12 1 1.20 5.80 E3 E1 E 9.70 ai14911b 48 Pin 1 identification 13 1 12 5B_ME 1. Drawing is not to scale. 2. Dimensions are in millimeters. Table 53.
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STM32F103x8, STM32F103xB 6.2 Package characteristics Thermal characteristics The maximum chip junction temperature (TJmax) must never exceed the values given in Table 8: General operating conditions on page 31.
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Package characteristics 6.2.2 STM32F103x8, STM32F103xB Selecting the product temperature range When ordering the microcontroller, the temperature range is specified in the ordering information scheme shown in Table 55: Ordering information scheme. Each temperature range suffix corresponds to a specific guaranteed ambient temperature at maximum dissipation and, to a specific maximum junction temperature.
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STM32F103x8, STM32F103xB Package characteristics Using the values obtained in Table 54 TJmax is calculated as follows: – For LQFP100, 46 °C/W TJmax = 115 °C + (46 °C/W × 134 mW) = 115 °C + 6.2 °C = 121.2 °C This is within the range of the suffix 7 version parts (–40 < TJ < 125 °C). In this case, parts must be ordered at least with the temperature range suffix 7 (see Table 55: Ordering information scheme). Figure 43. LQFP100 PD max vs.
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Ordering information scheme 7 STM32F103x8, STM32F103xB Ordering information scheme Table 55.
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STM32F103x8, STM32F103xB 8 Revision history Revision history Table 56. Document revision history Date Revision 01-jun-2007 1 Initial release. 2 Flash memory size modified in Note 6, Note 4, Note 7, Note 7 and BGA100 pins added to Table 4: Medium-density STM32F103xx pin definitions. Figure 3: STM32F103xx performance line BGA100 ballout added. THSE changed to TLSE in Figure 19: Low-speed external clock source AC timing diagram. VBAT ranged modified in Power supply schemes.
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Revision history Table 56. STM32F103x8, STM32F103xB Document revision history (continued) Date 18-Oct-2007 80/84 Revision Changes 3 STM32F103CBT6, STM32F103T6 and STM32F103T8 root part numbers added (see Table 2: STM32F103xx medium-density device features and peripheral counts) VFQFPN36 package added (see Section 6: Package characteristics). All packages are ECOPACK® compliant.
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STM32F103x8, STM32F103xB Table 56. Revision history Document revision history (continued) Date 22-Nov-2007 Revision Changes 4 Document status promoted from preliminary data to datasheet. The STM32F103xx is USB certified. Small text changes. Power supply schemes on page 11 modified. Number of communication peripherals corrected for STM32F103Tx and number of GPIOs corrected for LQFP package in Table 2: STM32F103xx mediumdensity device features and peripheral counts.
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Revision history Table 56. STM32F103x8, STM32F103xB Document revision history (continued) Date 14-Mar-2008 21-Mar-2008 22-May-2008 82/84 Revision Changes 5 Figure 2: Clock tree on page 17 added. Maximum TJ value given in Table 7: Thermal characteristics on page 31. CRC feature added (see CRC (cyclic redundancy check) calculation unit on page 9 and Figure 8: Memory map on page 27 for address). IDD modified in Table 15: Typical and maximum current consumptions in Stop and Standby modes.
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STM32F103x8, STM32F103xB Table 56. Revision history Document revision history (continued) Date 21-Jul-2008 22-Sep-2008 Revision Changes 8 Power supply supervisor updated and VDDA added to Table 8: General operating conditions. Capacitance modified in Figure 11: Power supply scheme on page 29. Table notes revised in Section 5: Electrical characteristics. Table 15: Typical and maximum current consumptions in Stop and Standby modes modified.
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