Datasheet

Revision history STM32F103x4, STM32F103x6
96/99 DocID15060 Rev 7
8 Revision history
Table 59. Document revision history
Date Revision Changes
22-Sep-2008 1
Initial release.
30-Mar-2009 2
“96-bit unique ID” feature added and I/O information clarified on page 1.
Timers specified on page 1 (Motor control capability mentioned).
Table 4: Timer feature comparison added.
PB4, PB13, PB14, PB15, PB3/TRACESWO moved from Default column to Remap
column, plus small additional changes in
Table 5: Low-density STM32F103xx pin
definitions.
Figure 8: Memory map modified.
References to V
REF-
removed:
– Figure 1: STM32F103xx performance line block diagram modified,
– Figure 11: Power supply scheme modified
– Figure 34: ADC accuracy characteristics modified
– Note modified in Table 49: ADC accuracy.
Table 20: High-speed external user clock characteristics and Table 21: Low-speed
external user clock characteristics modified.
Note modified in Table 13: Maximum current consumption in Run mode, code with
data processing running from Flash and Table 15: Maximum current consumption
in Sleep mode, code running from Flash or RAM.
Figure 17 shows a typical curve (title modified). ACC
HSI
max values modified in
Table 24: HSI oscillator characteristics.
TFBGA64 package added (see Table 54 and Table 47).
Small text changes.
24-Sep-2009 3
Note 5 updated and Note 4 added in Table 5: Low-density STM32F103xx pin
definitions.
V
RERINT
and T
Coeff
added to Table 12: Embedded internal reference voltage.
Typical I
DD_VBAT
value added in Table 16: Typical and maximum current
consumptions in Stop and Standby modes. Figure 15: Typical current consumption
on V
BAT
with RTC on versus temperature at different V
BAT
values added.
f
HSE_ext
min modified in Table 20: High-speed external user clock characteristics.
C
L1
and C
L2
replaced by C in Table 22: HSE 4-16 MHz oscillator characteristics
and Table 23: LSE oscillator characteristics (f
LSE
= 32.768 kHz), notes modified
and moved below the tables. Table 24: HSI oscillator characteristics modified.
Conditions removed from Table 26: Low-power mode wakeup timings.
Note 1 modified below Figure 21: Typical application with an 8 MHz crystal.
Figure 28: Recommended NRST pin protection modified.
Jitter added to Table 27: PLL characteristics on page 52.
IEC 1000 standard updated to IEC 61000 and SAE J1752/3 updated to IEC 61967-
2 in
Section 5.3.10: EMC characteristics on page 53.
C
ADC
and R
AIN
parameters modified in Table 46: ADC characteristics. R
AIN
max
values modified in Table 47: R
AIN
max for f
ADC
= 14 MHz.
Small text changes.