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ManualsBrandsST ManualsEmbedded Processors & ControllersMicrocontroller 32bit 256KB LQFP

This is information on a product in full production.

March 2015 DocID15081 Rev 8 1/105

STM32F100xC STM32F100xD

STM32F100xE

High-density value line, advanced ARM

-based 32-bit MCU with

256 to 512 KB Flash, 16 timers, ADC, DAC & 11 comm interfaces

Datasheet − production data

Features

• Core: ARM

32-bit Cortex

-M3

CPU

– 24 MHz maximum frequency, 1.25 DMIPS

/MHz (Dhrystone 2.1) performance

– Single-cycle multiplication and hardware

division

• Memories

– 256 to 512 Kbytes of Flash memory

– 24 to 32 Kbytes of SRAM

– Flexible static memory controller with 4

Chip Selects. Supports SRAM, PSRAM

and NOR memories

– LCD parallel interface, 8080/6800 modes

• Clock, reset and supply management

– 2.0 to 3.6 V application supply and I/Os

– POR, PDR and programmable voltage

detector (PVD)

– 4-to-24 MHz crystal oscillator

– Internal 8 MHz factory-trimmed RC

– Internal 40 kHz RC

– PLL for CPU clock

– 32 kHz oscillator for RTC with calibration

• Low power

– Sleep, Stop and Standby modes

–V

BAT

supply for RTC and backup registers

• Serial wire debug (SWD) and JTAG I/F

• DMA

– 12-channel DMA controller

– Peripherals supported: timers, ADC, SPIs,

Cs, USARTs and DACs

• 1 × 12-bit, 1.2 µs A/D converter (up to 16 ch.)

– Conversion range: 0 to 3.6 V

– Temperature sensor

• 2 × 12-bit D/A converters

• Up to 112 fast I/O ports

– 51/80/112 I/Os, all mappable on 16

external interrupt vectors and almost all

5 V-tolerant

• Up to 16 timers

– Up to seven 16-bit timers, each with up to 4

IC/OC/PWM or pulse counter

– One 16-bit, 6-channel advanced-control

timer: up to 6 channels for PWM output,

dead time generation and emergency stop

– One 16-bit timer, with 2 IC/OC, 1

OCN/PWM, dead-time generation and

emergency stop

– Two 16-bit timers, each with

IC/OC/OCN/PWM, dead-time generation

and emergency stop

– Two watchdog timers

– SysTick timer: 24-bit downcounter

– Two 16-bit basic timers to drive the DAC

• Up to 11 communications interfaces

– Up to two I

C interfaces (SMBus/PMBus)

– Up to 3 USARTs (ISO 7816 interface, LIN,

IrDA capability, modem control)

– Up to 2 UARTs

– Up to 3 SPIs (12 Mbit/s)

– Consumer electronics control (CEC) I/F

• CRC calculation unit, 96-bit unique ID

Table 1. Device summary

Reference Part number

STM32F100xC

STM32F100RC, STM32F100VC,

STM32F100ZC

STM32F100xD

STM32F100RD, STM32F100VD,

STM32F100ZD

STM32F100xE

STM32F100RE, STM32F100VE,

STM32F100ZE

LQFP100

14 × 14 mm

LQFP144

20 × 20 mm

LQFP64

10 × 10 mm

www.st.com

Summary of content (105 pages)

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STM32F100xC STM32F100xD STM32F100xE High-density value line, advanced ARM®-based 32-bit MCU with 256 to 512 KB Flash, 16 timers, ADC, DAC & 11 comm interfaces Datasheet −production data Features • Core: ARM® 32-bit Cortex®-M3 CPU – 24 MHz maximum frequency, 1.25 DMIPS /MHz (Dhrystone 2.1) performance – Single-cycle multiplication and hardware division • Memories – 256 to 512 Kbytes of Flash memory – 24 to 32 Kbytes of SRAM – Flexible static memory controller with 4 Chip Selects.
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Contents STM32F100xC, STM32F100xD, STM32F100xE Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3 2/105 2.1 Device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 2.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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STM32F100xC, STM32F100xD, STM32F100xE Contents 4 Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 5 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 5.1 6 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 5.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 5.1.2 Typical values . . . . . . . .
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Contents STM32F100xC, STM32F100xD, STM32F100xE 6.2.1 Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 6.2.2 Selecting the product temperature range . . . . . . . . . . . . . . . . . . . . . . 100 7 Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 8 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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STM32F100xC, STM32F100xD, STM32F100xE List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. Table 43. Table 44.
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List of tables Table 45. Table 46. Table 47. Table 48. Table 49. Table 50. Table 51. Table 52. Table 53. Table 54. Table 55. Table 56. Table 57. Table 58. Table 59. Table 60. Table 61. Table 62. 6/105 STM32F100xC, STM32F100xD, STM32F100xE I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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STM32F100xC, STM32F100xD, STM32F100xE List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Figure 38. Figure 39. Figure 40.
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List of figures Figure 46. Figure 47. 8/105 STM32F100xC, STM32F100xD, STM32F100xE LQFP64 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 LQFP100 PD max vs. TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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STM32F100xC, STM32F100xD, STM32F100xE 1 Introduction Introduction This datasheet provides the ordering information and mechanical device characteristics of the STM32F100xC, STM32F100xD and STM32F100xE value line microcontrollers. In the rest of the document, the STM32F100xC, STM32F100xD and STM32F100xE are referred to as high-density value line devices.
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Description 2 STM32F100xC, STM32F100xD, STM32F100xE Description The STM32F100xx value line family incorporates the high-performance ARM® Cortex®-M3 32-bit RISC core operating at a 24 MHz frequency, high-speed embedded memories (Flash memory up to 512 Kbytes and SRAM up to 32 Kbytes), a flexible static memory control (FSMC) interface (for devices offered in packages of 100 pins and more) and an extensive range of enhanced peripherals and I/Os connected to two APB buses.
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STM32F100xC, STM32F100xD, STM32F100xE 2.1 Description Device overview Table 2.
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Description STM32F100xC, STM32F100xD, STM32F100xE Figure 1. STM32F100xx value line block diagram Ibus Cortex-M3 CPU Fmax : 24 MHz NVIC GP DMA Power VDD18 Voltage reg. 3.3 V to 1.8 V Flash 512 KB 32 bit SRAM 32 KB POR Reset Supply supervision Int POR / PDR @VDDA RC HS @VDDA 12 channels 80 AF EXT.
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STM32F100xC, STM32F100xD, STM32F100xE Description Figure 2.
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Description STM32F100xC, STM32F100xD, STM32F100xE 2.2 Overview 2.2.1 ARM® Cortex®-M3 core with embedded Flash and SRAM The ARM Cortex®-M3 processor is the latest generation of ARM processors for embedded systems. It has been developed to provide a low-cost platform that meets the needs of MCU implementation, with a reduced pin count and low-power consumption, while delivering outstanding computational performance and an advanced system response to interrupts.
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STM32F100xC, STM32F100xD, STM32F100xE Description specific LCD interfaces. This LCD parallel interface capability makes it easy to build costeffective graphic applications using LCD modules with embedded controllers or highperformance solutions using external controllers with dedicated acceleration. 2.2.
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Description STM32F100xC, STM32F100xD, STM32F100xE The boot loader is located in System Memory. It is used to reprogram the Flash memory by using USART1. For further details please refer to AN2606. 2.2.11 2.2.12 Power supply schemes • VDD = 2.0 to 3.6 V: External power supply for I/Os and the internal regulator. Provided externally through VDD pins. • VSSA, VDDA = 2.0 to 3.6 V: External analog power supplies for ADC, DAC, Reset blocks, RCs and PLL (minimum voltage to be applied to VDDA is 2.
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STM32F100xC, STM32F100xD, STM32F100xE Description either in normal or in low power mode. The device can be woken up from Stop mode by any of the EXTI line. The EXTI line source can be one of the 16 external lines, the PVD output or the RTC alarm. • Standby mode The Standby mode is used to achieve the lowest power consumption. The internal voltage regulator is switched off so that the entire 1.8 V domain is powered off. The PLL, the HSI RC and the HSE crystal oscillators are also switched off.
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Description STM32F100xC, STM32F100xD, STM32F100xE Table 3.
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STM32F100xC, STM32F100xD, STM32F100xE Description TIM2, TIM3, TIM4, TIM5 STM32F100xx devices feature four synchronizable 4-channel general-purpose timers. These timers are based on a 16-bit auto-reload up/downcounter and a 16-bit prescaler. They feature 4 independent channels each for input capture/output compare, PWM or onepulse mode output. This gives up to 12 input captures/output compares/PWMs on the largest packages.
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Description STM32F100xC, STM32F100xD, STM32F100xE Window watchdog The window watchdog is based on a 7-bit downcounter that can be set as free running. It can be used as a watchdog to reset the device when a problem occurs. It is clocked from the main clock. It has an early warning interrupt capability and the counter can be frozen in debug mode. SysTick timer This timer is dedicated for OS, but could also be used as a standard down counter. It features: 2.2.
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STM32F100xC, STM32F100xD, STM32F100xE Description HDMI (high-definition multimedia interface) consumer electronics control (CEC) The STM32F100xx value line embeds a HDMI-CEC controller that provides hardware support of consumer electronics control (CEC) (Appendix supplement 1 to the HDMI standard). This protocol provides high-level control functions between all audiovisual products in an environment. It is specified to operate at low speeds with minimum processing and memory overhead. 2.2.
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Description STM32F100xC, STM32F100xD, STM32F100xE This dual digital Interface supports the following features: • two DAC converters: one for each output channel • up to 10-bit output • left or right data alignment in 12-bit mode • synchronized update capability • noise-wave generation • triangular-wave generation • dual DAC channels’ independent or simultaneous conversions • DMA capability for each channel • external triggers for conversion • input voltage reference VREF+ Eight DAC trig
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STM32F100xC, STM32F100xD, STM32F100xE 3 Pinouts and pin descriptions Pinouts and pin descriptions 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 VDD_3 VSS_3 PE1 PE0 PB9 PB8 BOOT0 PB7 PB6 PB5 PB4 PB3 PG15 VDD_11 VSS_11 PG14 PG13 PG12 PG11 PG10 PG9 PD7 PD6 VDD_10 VSS_10 PD5 PD4 PD3 PD2 PD1 PD0 PC12 PC11 PC10 PA15 PA14 Figure 3.
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Pinouts and pin descriptions STM32F100xC, STM32F100xD, STM32F100xE 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 VDD_3 VSS_3 PE1 PE0 PB9 PB8 BOOT0 PB7 PB6 PB5 PB4 PB3 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 PC12 PC11 PC10 PA15 PA14 Figure 4.
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STM32F100xC, STM32F100xD, STM32F100xE Pinouts and pin descriptions VDD_3 VSS_3 PB9 PB8 BOOT0 PB7 PB6 PB5 PB4 PB3 PD2 PC12 PC11 PC10 PA15 PA14 Figure 5.
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Pinouts and pin descriptions STM32F100xC, STM32F100xD, STM32F100xE Table 4.
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STM32F100xC, STM32F100xD, STM32F100xE Pinouts and pin descriptions Table 4.
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Pinouts and pin descriptions STM32F100xC, STM32F100xD, STM32F100xE Table 4.
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STM32F100xC, STM32F100xD, STM32F100xE Pinouts and pin descriptions Table 4.
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Pinouts and pin descriptions STM32F100xC, STM32F100xD, STM32F100xE Table 4.
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STM32F100xC, STM32F100xD, STM32F100xE Pinouts and pin descriptions 3. Function availability depends on the chosen device. 4. If several peripherals share the same I/O pin, to avoid conflict between these alternate functions only one peripheral should be enabled at a time through the peripheral clock enable bit (in the corresponding RCC peripheral clock enable register). 5. PC13, PC14 and PC15 are supplied through the power switch.
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Pinouts and pin descriptions STM32F100xC, STM32F100xD, STM32F100xE Table 5.
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STM32F100xC, STM32F100xD, STM32F100xE Pinouts and pin descriptions Table 5. FSMC pin definition (continued) FSMC LQFP100(1) Pins NOR/PSRAM/SRAM NOR/PSRAM Mux PG10 NE3 NE3 - PG11 - - - PG12 NE4 NE4 - PG13 A24 A24 - PG14 A25 A25 - PB7 NADV NADV Yes PE0 NBL0 NBL0 Yes PE1 NBL1 NBL1 Yes 1. Ports F and G are not available in devices delivered in 100-pin packages.
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Memory mapping 4 STM32F100xC, STM32F100xD, STM32F100xE Memory mapping The memory map is shown in Figure 6. Figure 6.
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STM32F100xC, STM32F100xD, STM32F100xE 5 Electrical characteristics 5.1 Parameter conditions Electrical characteristics Unless otherwise specified, all voltages are referenced to VSS. 5.1.
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Electrical characteristics STM32F100xC, STM32F100xD, STM32F100xE Figure 7. Pin loading conditions Figure 8. Pin input voltage STM32F10xxx pin STM32F10xxx pin C = 50 pF VIN ai14123b ai14124b 5.1.6 Power supply scheme Figure 9. Power supply scheme 9%$7 %DFNXS FLUFXLWU\ 26& . 57& :DNH XS ORJLF %DFNXS UHJLVWHUV 287 *3 , 2V ,1 /HYHO VKLIWHU 3R ZHU VZL WFK 9 ,2 /RJLF .
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STM32F100xC, STM32F100xD, STM32F100xE 5.1.7 Electrical characteristics Current consumption measurement Figure 10. Current consumption measurement scheme IDD_VBAT VBAT IDD VDD VDDA ai14126 5.2 Absolute maximum ratings Stresses above the absolute maximum ratings listed in Table 6: Voltage characteristics, Table 7: Current characteristics, and Table 8: Thermal characteristics may cause permanent damage to the device.
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Electrical characteristics STM32F100xC, STM32F100xD, STM32F100xE Table 7. Current characteristics Symbol IVDD IVSS IIO Ratings Max.
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STM32F100xC, STM32F100xD, STM32F100xE Electrical characteristics Table 9.
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Electrical characteristics 5.3.3 STM32F100xC, STM32F100xD, STM32F100xE Embedded reset and power control block characteristics The parameters given in Table 11 are derived from tests performed under the ambient temperature and VDD supply voltage conditions summarized in Table 9. . Table 11.
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STM32F100xC, STM32F100xD, STM32F100xE 5.3.4 Electrical characteristics Embedded reference voltage The parameters given in Table 12 are derived from tests performed under the ambient temperature and VDD supply voltage conditions summarized in Table 9. Table 12. Embedded internal reference voltage Symbol VREFINT Parameter Internal reference voltage Conditions Min Typ –40 °C < TA < +105 °C 1.16 1.20 1.26 V –40 °C < TA < +85 °C 1.16 1.20 1.24 V 5.1 17.
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Electrical characteristics STM32F100xC, STM32F100xD, STM32F100xE Table 13. Maximum current consumption in Run mode, code with data processing running from Flash Max(1) Symbol Parameter Conditions External clock (2), all peripherals enabled IDD Supply current in Run mode External clock(2), all peripherals disabled HSI clock(2), all peripherals enabled HSI clock(2), all peripherals disabled fHCLK Unit TA = 85 °C TA = 105 °C 24 MHz 19.7 20 16 MHz 14.6 14.7 8 MHz 8.2 8.6 24 MHz 11.3 11.
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STM32F100xC, STM32F100xD, STM32F100xE Electrical characteristics Table 15. STM32F100xxB maximum current consumption in Sleep mode, code running from Flash or RAM Max(1) Symbol Parameter Conditions External clock(2) all peripherals enabled External clock(2), all peripherals disabled IDD Supply current in Sleep mode HSI clock(2), all peripherals enabled HSI clock(2), all peripherals disabled fHCLK Unit TA = 85 °C TA = 105 °C 24 MHz 14.1 14.3 16 MHz 9.7 10.3 8 MHz 5.9 6.2 24 MHz 4.2 4.
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Electrical characteristics STM32F100xC, STM32F100xD, STM32F100xE Table 16. Typical and maximum current consumptions in Stop and Standby modes Typ(1) Symbol Parameter Conditions Max VDD/VBAT VDD/ VBAT VDD/VBAT TA = TA = = 2.0 V = 2.4 V = 3.
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STM32F100xC, STM32F100xD, STM32F100xE Electrical characteristics Table 17. Typical current consumption in Run mode, code with data processing running from Flash Typical values(1) Symbol Parameter Conditions Running on high-speed external clock with an 8 MHz crystal(3) IDD Supply current in Run mode Running on high-speed internal RC (HSI) fHCLK All peripherals All peripherals enabled(2) disabled 24 MHz 14.1 9.5 16 MHz 10 6.85 8 MHz 5.8 4.05 4 MHz 3.6 2.65 2 MHz 2.3 1.85 1 MHz 1.
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Electrical characteristics STM32F100xC, STM32F100xD, STM32F100xE Table 18. Typical current consumption in Sleep mode, code running from Flash or RAM Typical values(1) Symbol Parameter Conditions Running on high-speed external clock with an 8 MHz crystal(3) IDD Supply current in Sleep mode Running on high-speed internal RC (HSI) fHCLK All peripherals All peripherals enabled(2) disabled 24 MHz 8.7 2.75 16 MHz 6.1 2.1 8 MHz 3.3 1.3 4 MHz 2.25 1.2 2 MHz 1.65 1.15 1 MHz 1.35 1.
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STM32F100xC, STM32F100xD, STM32F100xE Electrical characteristics On-chip peripheral current consumption The current consumption of the on-chip peripherals is given in Table 19.
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Electrical characteristics STM32F100xC, STM32F100xD, STM32F100xE Table 19. Peripheral current consumption (continued) APB2 Peripheral Typical consumption at 25 °C(1) GPIO A 0.26 GPIO B 0.26 GPIO C 0.26 GPIO D 0.26 GPIO E 0.26 GPIO F 0.24 GPIO G 0.25 (3) 1.28 ADC1 SPI1 0.2 USART1 0.37 TIM1 0.63 TIM15 0.43 TIM16 0.34 TIM17 0.34 Unit mA 1. fHCLK = fAPB1 = fAPB2 = 24 MHz, default prescaler value for each peripheral. 2.
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STM32F100xC, STM32F100xD, STM32F100xE Electrical characteristics Table 20. High-speed external user clock characteristics Symbol Parameter DuCy(HSE) Duty cycle IL Conditions Min (1) Typ 45 OSC_IN Input leakage current VSS ≤VIN ≤VDD Max Unit 55 % ±1 µA 1. Guaranteed by design, not tested in production.
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Electrical characteristics STM32F100xC, STM32F100xD, STM32F100xE Figure 12. Low-speed external clock source AC timing diagram VLSEH 90% VLSEL 10% tr(LSE) tf(LSE) tW(LSE) OSC32_IN IL t tW(LSE) TLSE External clock source fLSE_ext STM32F10xxx ai14140c High-speed external clock generated from a crystal/ceramic resonator The high-speed external (HSE) clock can be supplied with a 4 to 24 MHz crystal/ceramic resonator oscillator.
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STM32F100xC, STM32F100xD, STM32F100xE Electrical characteristics 4. The relatively low value of the RF resistor offers a good protection against issues resulting from use in a humid environment, due to the induced leakage and the bias condition change. However, it is recommended to take this point into account if the MCU is used in tough humidity conditions. 5. tSU(HSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz oscillation is reached.
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Electrical characteristics STM32F100xC, STM32F100xD, STM32F100xE Table 23. LSE oscillator characteristics (fLSE = 32.768 kHz)(1) Symbol RF Parameter Conditions Min Typ Feedback resistor Max Unit 5 MΩ Recommended load capacitance versus equivalent serial resistance of the crystal (RS)(3) RS = 30 KΩ 15 pF I2 LSE driving current VDD = 3.3 V VIN = VSS 1.4 µA gm Oscillator transconductance CL1 CL2(2) tSU(LSE)(4) 5 VDD is stabilized Startup time µA/V TA = 50 °C 1.5 TA = 25 °C 2.
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STM32F100xC, STM32F100xD, STM32F100xE Electrical characteristics High-speed internal (HSI) RC oscillator Table 24. HSI oscillator characteristics(1) Symbol fHSI Parameter Conditions Min Frequency TA = –40 to 105 °C Accuracy of HSI oscillator % TA = –10 to 85 °C -2.2 1.3 % (2) -1.9 1.3 % -1 1 % 1 2 µs 100 µA TA = 25 °C HSI oscillator startup time (3) HSI oscillator power consumption IDD(HSI) MHz 2.5 TA = 0 to 70 °C (3) Unit -2.4 (2) tsu(HSI) Max 8 (2) ACCHSI Typ 80 1.
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Electrical characteristics STM32F100xC, STM32F100xD, STM32F100xE 1. The wakeup times are measured from the wakeup event to the point at which the user application code reads the first instruction. 5.3.8 PLL characteristics The parameters given in Table 27 are derived from tests performed under the ambient temperature and VDD supply voltage conditions summarized in Table 9. Table 27. PLL characteristics Value Symbol Parameter Unit Min(1) Typ Max(1) PLL input clock(2) 1 8.
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STM32F100xC, STM32F100xD, STM32F100xE Electrical characteristics Table 29. Flash memory endurance and data retention Value Symbol NEND tRET Parameter Endurance Conditions Min(1) TA = –40 to +85 °C (6 suffix versions) TA = –40 to +105 °C (7 suffix versions) 10 1 kcycle(2) at TA = 85 °C 30 Data retention 1 kcycle(2) at TA = 105 °C 10 kcycles(2) at TA = 55 °C 10 Unit Typ Max kcycles Years 20 1. Based on characterization not tested in production. 2.
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Electrical characteristics STM32F100xC, STM32F100xD, STM32F100xE Figure 15. Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms )60&B1( W Y 12(B1( W Z 12( W K 1(B12( )60&B12( )60&B1:( WY $B1( )60&B$> @ W K $B12( $GGUHVV WY %/B1( W K %/B12( )60&B1%/> @ W K 'DWDB1( W VX 'DWDB12( WK 'DWDB12( W VX 'DWDB1( 'DWD )60&B'> @ W Y 1$'9B1( WZ 1$'9 )60&B1$'9 06 9 1. Mode 2/B, C and D only. In Mode 1, FSMC_NADV is not used.
PAGE 57
STM32F100xC, STM32F100xD, STM32F100xE Electrical characteristics Table 30. Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings(1) (2) Symbol Parameter Min Max Unit tw(NE) FSMC_NE low time 5THCLK – 1.5 5THCLK + 2 ns tv(NOE_NE) FSMC_NEx low to FSMC_NOE low 0.5 1.5 ns tw(NOE) FSMC_NOE low time 5THCLK – 1.5 5THCLK + 1.5 ns th(NE_NOE) FSMC_NOE high to FSMC_NE high hold time –1.
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Electrical characteristics STM32F100xC, STM32F100xD, STM32F100xE Figure 16. Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms tw(NE) FSMC_NEx FSMC_NOE tv(NWE_NE) tw(NWE) t h(NE_NWE) FSMC_NWE tv(A_NE) FSMC_A[25:0] th(A_NWE) Address tv(BL_NE) FSMC_NBL[3:0] th(BL_NWE) NBL tv(Data_NE) th(Data_NWE) Data FSMC_D[15:0] t v(NADV_NE) tw(NADV) FSMC_NADV(1) ai14990 1. Mode 2/B, C and D only. In Mode 1, FSMC_NADV is not used. Table 31.
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STM32F100xC, STM32F100xD, STM32F100xE Electrical characteristics Figure 17. Asynchronous multiplexed PSRAM/NOR read waveforms tw(NE) FSMC_NE tv(NOE_NE) t h(NE_NOE) FSMC_NOE t w(NOE) FSMC_NWE tv(A_NE) FSMC_A[25:16] t h(A_NOE) Address tv(BL_NE) th(BL_NOE) FSMC_NBL[1:0] NBL th(Data_NE) tsu(Data_NE) t v(A_NE) tsu(Data_NOE) Address FSMC_AD[15:0] t v(NADV_NE) th(Data_NOE) Data th(AD_NADV) tw(NADV) FSMC_NADV ai14892b Table 32.
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Electrical characteristics STM32F100xC, STM32F100xD, STM32F100xE Figure 18. Asynchronous multiplexed PSRAM/NOR write waveforms tw(NE) FSMC_NEx FSMC_NOE tv(NWE_NE) tw(NWE) t h(NE_NWE) FSMC_NWE tv(A_NE) FSMC_A[25:16] th(A_NWE) Address tv(BL_NE) th(BL_NWE) FSMC_NBL[1:0] NBL t v(A_NE) t v(Data_NADV) Address FSMC_AD[15:0] t v(NADV_NE) th(Data_NWE) Data th(AD_NADV) tw(NADV) FSMC_NADV ai14891B Table 33.
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STM32F100xC, STM32F100xD, STM32F100xE Electrical characteristics Synchronous waveforms and timings Figure 19 through Figure 22 represent synchronous waveforms and Table 35 through Table 37 provide the corresponding timings.
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Electrical characteristics STM32F100xC, STM32F100xD, STM32F100xE Table 34. Synchronous multiplexed NOR/PSRAM read timings(1)(2) Symbol Parameter Max Unit tw(CLK) FSMC_CLK period td(CLKL-NExL) FSMC_CLK low to FSMC_NEx low (x = 0...2) td(CLKL-NExH) FSMC_CLK low to FSMC_NEx high (x = 0...2) td(CLKL-NADVL) FSMC_CLK low to FSMC_NADV low td(CLKL-NADVH) FSMC_CLK low to FSMC_NADV high td(CLKL-AV) FSMC_CLK low to FSMC_Ax valid (x = 16...25) td(CLKL-AIV) FSMC_CLK low to FSMC_Ax invalid (x = 16...
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STM32F100xC, STM32F100xD, STM32F100xE Electrical characteristics Figure 20. Synchronous multiplexed PSRAM write timings "53452. TW #,+ TW #,+ &3-#?#,+ $ATA LATENCY TD #,+, .%X, TD #,+, .%X( &3-#?.%X TD #,+, .!$6, TD #,+, .!$6( &3-#?.!$6 TD #,+, !6 TD #,+, !)6 &3-#?!; = TD #,+, .7%, TD #,+, .7%( &3-#?.7% TD #,+, !$)6 TD #,+, $ATA TD #,+, $ATA TD #,+, !$6 !$; = &3-#?!$; = $ $ &3-#?.7!)4 7!)4#&' B 7!)40/, B TSU .7!)46 #,+( TH #,+( .7!)46 TD #,+, .",( &3-#?.
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Electrical characteristics STM32F100xC, STM32F100xD, STM32F100xE Table 35. Synchronous multiplexed PSRAM write timings(1)(2) Symbol Parameter Max Unit tw(CLK) FSMC_CLK period td(CLKL-NExL) FSMC_CLK low to FSMC_Nex low (x = 0...2) td(CLKL-NExH) FSMC_CLK low to FSMC_NEx high (x = 0...2) td(CLKL-NADVL) FSMC_CLK low to FSMC_NADV low td(CLKL-NADVH) FSMC_CLK low to FSMC_NADV high td(CLKL-AV) FSMC_CLK low to FSMC_Ax valid (x = 16...25) td(CLKL-AIV) FSMC_CLK low to FSMC_Ax invalid (x = 16...
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STM32F100xC, STM32F100xD, STM32F100xE Electrical characteristics Figure 21. Synchronous non-multiplexed NOR/PSRAM read timings "53452. TW #,+ TW #,+ &3-#?#,+ TD #,+, .%X, TD #,+, .%X( $ATA LATENCY &3-#?.%X TD #,+, .!$6, TD #,+, .!$6( &3-#?.!$6 TD #,+, !)6 TD #,+, !6 &3-#?!; = TD #,+( ./%, TD #,+, ./%( &3-#?./% TSU $6 #,+( TH #,+( $6 TSU $6 #,+( &3-#?$; = TH #,+( $6 $ TSU .7!)46 #,+( $ $ TH #,+( .7!)46 &3-#?.7!)4 7!)4#&' B 7!)40/, B TSU .7!)46 #,+( T H #,+( .
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Electrical characteristics STM32F100xC, STM32F100xD, STM32F100xE Figure 22. Synchronous non-multiplexed PSRAM write timings TW #,+ "53452. TW #,+ &3-#?#,+ TD #,+, .%X, TD #,+, .%X( $ATA LATENCY &3-#?.%X TD #,+, .!$6, TD #,+, .!$6( &3-#?.!$6 TD #,+, !6 TD #,+, !)6 &3-#?!; = TD #,+, .7%, TD #,+, .7%( &3-#?.7% TD #,+, $ATA &3-#?$; = TD #,+, $ATA $ $ &3-#?.7!)4 7!)4#&' B 7!)40/, B TSU .7!)46 #,+( TD #,+, .",( TH #,+( .7!)46 &3-#?.", AI I Table 37.
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STM32F100xC, STM32F100xD, STM32F100xE 5.3.11 Electrical characteristics EMC characteristics Susceptibility tests are performed on a sample basis during device characterization. Functional EMS (Electromagnetic susceptibility) While a simple application is executed on the device (toggling 2 LEDs through I/O ports). the device is stressed by two electromagnetic events until a failure occurs.
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Electrical characteristics STM32F100xC, STM32F100xD, STM32F100xE Electromagnetic Interference (EMI) The electromagnetic field emitted by the device is monitored while a simple application is executed (toggling 2 LEDs through the I/O ports). This emission test is compliant with IEC 61967-2 standard which specifies the test board and the pin loading. Table 39. EMI characteristics Symbol Parameter SEMI 5.3.12 Peak level Conditions Monitored frequency band Max vs. [fHSE/fHCLK] Unit 8/24 MHz 0.
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STM32F100xC, STM32F100xD, STM32F100xE 5.3.13 Electrical characteristics I/O current injection characteristics As a general rule, current injection to the I/O pins, due to external voltage below VSS or above VDD (for standard, 3 V-capable I/O pins) should be avoided during normal product operation.
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Electrical characteristics 5.3.14 STM32F100xC, STM32F100xD, STM32F100xE I/O port characteristics General input/output characteristics Unless otherwise specified, the parameters given in Table 43 are derived from tests performed under the conditions summarized in Table 9. All I/Os are CMOS and TTL compliant. Table 43. I/O static characteristics Symbol VIL VIH Vhys Ilkg Parameter Conditions Min Typ Max Standard I/O input low level voltage –0.3 0.28*(VDD–2 V)+0.
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STM32F100xC, STM32F100xD, STM32F100xE Electrical characteristics Figure 23. Standard I/O input characteristics - CMOS port 6)( 6), 6 6 $$ T 6 )( 3 STAND #-/ 7)(MIN 7),MAX 6 6 )( $$ IREMEN ARD REQU RD #-/3 STANDA )NPUT RANGE NOT GUARANTEED 6 6), $$ 6 6 $$ REQUIREMENT ), 6$$ 6 AI B Figure 24.
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Electrical characteristics STM32F100xC, STM32F100xD, STM32F100xE Figure 25. 5 V tolerant I/O input characteristics - CMOS port 6)( 6), 6 NDARD -/3 STA 6 $$ ENTS 6 )( REQUIREM # 6 ), 6 $$ 6 $$ QUIRMENT 6 ), DARD RE #-/3 STAN 6 )( 6 $$ )NPUT RANGE NOT GUARANTEED 6$$ 6 6$$ AI B Figure 26.
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STM32F100xC, STM32F100xD, STM32F100xE Electrical characteristics Output voltage levels Unless otherwise specified, the parameters given in Table 44 are derived from tests performed under the ambient temperature and VDD supply voltage conditions summarized in Table 9. All I/Os are CMOS and TTL compliant. Table 44.
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Electrical characteristics STM32F100xC, STM32F100xD, STM32F100xE Input/output AC characteristics The definition and values of input/output AC characteristics are given in Figure 27 and Table 45, respectively. Unless otherwise specified, the parameters given in Table 45 are derived from tests performed under the ambient temperature and VDD supply voltage conditions summarized in Table 9. Table 45.
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STM32F100xC, STM32F100xD, STM32F100xE Electrical characteristics Figure 27. I/O AC characteristics definition %84%2.!, /54054 /. P& TR )/ OUT TF )/ OUT 4 -AXIMUM FREQUENCY IS ACHIEVED IF T R TF 4 AND IF THE DUTY CYCLE IS WHEN LOADED BY P& AI C 5.3.15 NRST pin characteristics The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up resistor, RPU (see Table 43).
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Electrical characteristics STM32F100xC, STM32F100xD, STM32F100xE Figure 28. Recommended NRST pin protection VDD External reset circuit(1) NRST(2) RPU Internal Reset Filter 0.1 µF STM32F10xxx ai14132d 1. The reset network protects the device against parasitic resets. 2. The user must ensure that the level on the NRST pin can go below the VIL(NRST) max level specified in Table 46. Otherwise the reset will not be taken into account by the device.
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STM32F100xC, STM32F100xD, STM32F100xE 5.3.16 Electrical characteristics TIMx characteristics The parameters given in Table 47 are guaranteed by design. Refer to Section 5.3.13: I/O current injection characteristics for details on the input/output alternate function characteristics (output compare, input capture, external clock, PWM output). Table 47.
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Electrical characteristics STM32F100xC, STM32F100xD, STM32F100xE Table 48. I2C characteristics Standard mode I2C(1) Fast mode I2C(1)(2) Symbol Parameter Unit Min Max Min Max tw(SCLL) SCL clock low time 4.7 1.3 tw(SCLH) SCL clock high time 4.0 0.6 tsu(SDA) SDA setup time 250 100 th(SDA) SDA data hold time 0 0 tr(SDA) tr(SCL) SDA and SCL rise time 1000 300 tf(SDA) tf(SCL) SDA and SCL fall time 300 300 th(STA) Start condition hold time 4.0 0.
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STM32F100xC, STM32F100xD, STM32F100xE Electrical characteristics Figure 29. I2C bus AC waveforms and measurement circuit 9''B, & 9''B, & 5S 5S ,ð& EXV 670 ) [ 5V 6'$ 5V 6&/ 6WDUW UHSHDWHG 6WDUW 6WDUW WVX 67$ 6'$ WI 6'$ WU 6'$ WK 67$ WVX 6'$ WZ 6&// WK 6'$ WVX 672 67$ 6WRS 6&/ WZ 6&/+ WU 6&/ WI 6&/ WVX 672 DL I 1. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD. Table 49. SCL frequency (fPCLK1= 24 MHz, VDD = 3.3 V)(1)(2) I2C_CCR value fSCL (kHz)(3) RP = 4.
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Electrical characteristics STM32F100xC, STM32F100xD, STM32F100xE SPI interface characteristics Unless otherwise specified, the parameters given in Table 50 are preliminary values derived from tests performed under the ambient temperature, fPCLKx frequency and VDD supply voltage conditions summarized in Table 9. Refer to Section 5.3.13: I/O current injection characteristics for more details on the input/output alternate function characteristics (NSS, SCK, MOSI, MISO). Table 50.
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STM32F100xC, STM32F100xD, STM32F100xE Electrical characteristics Figure 30. SPI timing diagram - slave mode and CPHA = 0 E^^ ŝŶƉƵƚ ƚĐ;^ <Ϳ ƚŚ;E^^Ϳ ^ < /ŶƉƵƚ ƚ^h;E^^Ϳ W, сϬ WK>сϬ ƚǁ;^ <,Ϳ ƚǁ;^ <>Ϳ W, сϬ WK>сϭ ƚĂ;^KͿ D/^K KhdW hd ƚǀ;^KͿ ƚŚ;^KͿ D^ K hd /dϲ Khd D^ /E / dϭ /E ƚƌ;^ <Ϳ ƚĨ;^ <Ϳ ƚĚŝƐ;^KͿ >^ Khd ƚƐƵ;^/Ϳ DK^/ /EWhd >^ /E ƚŚ;^/Ϳ DL F Figure 31. SPI timing diagram - slave mode and CPHA = 1 166 LQSXW 6&. ,QSXW W68 166 &3+$ &32/ &3+$ &32/ WF 6&. WZ 6&.
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Electrical characteristics STM32F100xC, STM32F100xD, STM32F100xE Figure 32. SPI timing diagram - master mode (IGH .33 INPUT 3#+ /UTPUT #0(! #0/, 3#+ /UTPUT TC 3#+ #0(! #0/, #0(! #0/, #0(! #0/, TSU -) -)3/ ).0 54 TW 3#+( TW 3#+, TR 3#+ TF 3#+ -3 "). ") 4 ). ,3" ). TH -) -/3) /54054 - 3" /54 " ) 4 /54 TV -/ ,3" /54 TH -/ AI 6 1. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD. HDMI consumer electronics control (CEC) Refer to Section 5.3.
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STM32F100xC, STM32F100xD, STM32F100xE Electrical characteristics Table 51. ADC characteristics Symbol Parameter Conditions Min Typ Max Unit VDDA Power supply 2.4 3.6 V VREF+ Positive reference voltage 2.4 VDDA V IVREF Current on the VREF input pin 220(1) µA fADC ADC clock frequency 0.6 12 MHz fS(2) Sampling rate 0.
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Electrical characteristics STM32F100xC, STM32F100xD, STM32F100xE Table 52. RAIN max for fADC = 12 MHz(1) Ts (cycles) tS (µs) RAIN max (kΩ) 1.5 0.125 0.4 7.5 0.625 5.9 13.5 1.125 11.4 28.5 2.375 25.2 41.5 3.45 37.2 55.5 4.625 50 71.5 5.96 NA 239.5 20 NA 1. Guaranteed by design, not tested in production. Table 53.
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STM32F100xC, STM32F100xD, STM32F100xE Note: Electrical characteristics Any positive injection current within the limits specified for IINJ(PIN) and ΣIINJ(PIN) in Section 5.3.13 does not affect the ADC accuracy. Figure 33.
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Electrical characteristics STM32F100xC, STM32F100xD, STM32F100xE Figure 35. Power supply and reference decoupling (VREF+ not connected to VDDA) STM32F10xxx V REF+ 1 µF // 10 nF V DDA 1 µF // 10 nF V SSA/V REF- ai14380b 1. VREF+ is available on 100-pin packages and on TFBGA64 packages. VREF- is available on 100-pin packages only. Figure 36. Power supply and reference decoupling (VREF+ connected to VDDA) STM32F10xxx VREF+/VDDA 1 µF // 10 nF VREF–/VSSA ai14381b 1.
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STM32F100xC, STM32F100xD, STM32F100xE 5.3.19 Electrical characteristics DAC electrical specifications Table 55. DAC characteristics Symbol Parameter Min Typ Max(1) Unit VDDA Analog supply voltage 2.4 3.6 V VREF+ Reference supply voltage 2.4 3.
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Electrical characteristics STM32F100xC, STM32F100xD, STM32F100xE Table 55. DAC characteristics (continued) Max(1) Unit ±10 mV Offset error (difference between measured value at Code (0x800) and the ideal value = VREF+/2) Given for the DAC in 12-bit configuration ±3 LSB Given for the DAC in 10-bit at VREF+ = 3.6 V ±12 LSB Given for the DAC in 12-bit at VREF+ = 3.6 V Gain error ±0.
PAGE 89
STM32F100xC, STM32F100xD, STM32F100xE 5.3.20 Electrical characteristics Temperature sensor characteristics Table 56. TS characteristics Symbol TL(1) Min VSENSE linearity with temperature Avg_Slope (1) V25(1) tSTART(2) TS_temp Parameter (3)(2) Typ Max Unit ±1 ±2 °C Average slope 4.0 4.3 4.6 mV/°C Voltage at 25°C 1.32 1.41 1.50 V 10 µs 17.1 µs Startup time 4 ADC sampling time when reading the temperature 1. Guaranteed by characterization, not tested in production. 2.
PAGE 90
Package characteristics STM32F100xC, STM32F100xD, STM32F100xE 6 Package characteristics 6.1 Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. Figure 38. LQFP144 - 144-pin, 20 x 20 mm low-profile quad flat package outline C ! ! ! 3%!4).
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STM32F100xC, STM32F100xD, STM32F100xE Package characteristics Table 57. LQFP144 - 144-pin, 20 x 20 mm low-profile quad flat package mechanical data inches(1) millimeters Symbol Min Typ Max Min Typ Max A - - 1.600 - - 0.0630 A1 0.050 - 0.150 0.0020 - 0.0059 A2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.170 0.220 0.270 0.0067 0.0087 0.0106 c 0.090 - 0.200 0.0035 - 0.0079 D 21.800 22.000 22.200 0.8583 0.8661 0.8740 D1 19.800 20.000 20.200 0.7795 0.
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Package characteristics STM32F100xC, STM32F100xD, STM32F100xE Figure 39. LQFP144 - 144-pin, 20 x 20 mm low-profile quad flat package recommended footprint DL H Device marking for LQFP144 The following figure shows the device marking for the LQFP144 package. Figure 40.
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STM32F100xC, STM32F100xD, STM32F100xE Package characteristics Figure 41. LQFP100 – 14 x 14 mm 100 pin low-profile quad flat package outline MM C ! ! ! 3%!4).' 0,!.% # '!5'% 0,!.% $ ! + CCC # , $ , $ 0). )$%.4)&)#!4)/. % % % B E ,?-%?6 1. Drawing is not to scale. Table 58. LQPF100 - 100-pin, 14 x 14 mm low-profile quad flat package mechanical data inches(1) millimeters Symbol Min Typ Max Min Typ Max A - - 1.600 - - 0.
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Package characteristics STM32F100xC, STM32F100xD, STM32F100xE Table 58. LQPF100 - 100-pin, 14 x 14 mm low-profile quad flat package mechanical data (continued) inches(1) millimeters Symbol Min Typ Max Min Typ Max L 0.450 0.600 0.750 0.0177 0.0236 0.0295 L1 - 1.000 - - 0.0394 - k 0.0° 3.5° 7.0° 0.0° 3.5° 7.0° ccc - - 0.080 - - 0.0031 1. Values in inches are converted from mm and rounded to 4 decimal digits. Figure 42.
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STM32F100xC, STM32F100xD, STM32F100xE Package characteristics Device marking for LQFP100 The following figure shows the device marking for the LQFP100 package. Figure 43.LQFP100 marking example (package top view) 2SWLRQDO JDWH PDUN 3URGXFW LGHQWLILFDWLRQ ^dDϯϮ&ϭϬϬ s dϲ 5HYLVLRQ FRGH y 'DWH FRGH z tt 3LQ LGHQWLILHU 06Y 9 1.
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Package characteristics STM32F100xC, STM32F100xD, STM32F100xE Figure 44.LQFP64 – 10 x 10 mm 64 pin low-profile quad flat package outline PP *$8*( 3/$1( F $ $ $ 6($7,1* 3/$1( & $ FFF & ' ' ' . / / 3,1 ,'(17,),&$7,21 ( ( ( E H :B0(B9 1. Drawing is not in scale. Table 59. LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat package mechanical data inches(1) millimeters Symbol 96/105 Min Typ Max Min Typ Max A - - 1.600 - - 0.
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STM32F100xC, STM32F100xD, STM32F100xE Package characteristics Table 59. LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat package mechanical data (continued) inches(1) millimeters Symbol Min Typ Max Min Typ Max K 0° 3.5° 7° 0° 3.5° 7° L 0.450 0.600 0.750 0.0177 0.0236 0.0295 L1 - 1.000 - - 0.0394 - ccc - - 0.080 - - 0.0031 1. Values in inches are converted from mm and rounded to 4 decimal digits. Figure 45.
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Package characteristics STM32F100xC, STM32F100xD, STM32F100xE Device marking for LQFP64 The following figure shows the device marking for the LQFP64 package. Figure 46.LQFP64 marking example (package top view) 5HYLVLRQ FRGH 3URGXFW LGHQWLILFDWLRQ y ^dDϯϮ&ϭϬϬ Z dϲ z tt 3LQ LGHQWLILHU 'DWH FRGH 06Y 9 1.
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STM32F100xC, STM32F100xD, STM32F100xE 6.2 Package characteristics Thermal characteristics The maximum chip junction temperature (TJmax) must never exceed the values given in Table 9: General operating conditions on page 38.
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Package characteristics 6.2.2 STM32F100xC, STM32F100xD, STM32F100xE Selecting the product temperature range When ordering the microcontroller, the temperature range is specified in the ordering information scheme shown in Table 61: Ordering information scheme. Each temperature range suffix corresponds to a specific guaranteed ambient temperature at maximum dissipation and, to a specific maximum junction temperature.
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STM32F100xC, STM32F100xD, STM32F100xE Package characteristics Using the values obtained in Table 60 TJmax is calculated as follows: – For LQFP100, 40 °C/W TJmax = 115 °C + (40 °C/W × 134 mW) = 115 °C + 5.4 °C = 120.4 °C This is within the range of the suffix 7 version parts (–40 < TJ < 125 °C). In this case, parts must be ordered at least with the temperature range suffix 7 (see Table 61: Ordering information scheme). Figure 47. LQFP100 PD max vs.
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Ordering information scheme 7 STM32F100xC, STM32F100xD, STM32F100xE Ordering information scheme Table 61.
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STM32F100xC, STM32F100xD, STM32F100xE 8 Revision history Revision history Table 62. Document revision history Date Revision 09-Oct-2008 1 Initial release. 31-Mar-2009 2 I/O information clarified on page 1. Table 5: High-density STM32F100xx pin definitions modified. Figure 5: Memory map on page 26 modified.
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Revision history STM32F100xC, STM32F100xD, STM32F100xE Table 62. Document revision history (continued) Date 08-Jun-2012 17-Sep-2012 10-Mar-2015 104/105 Revision Changes 6 Updated Table 7: Current characteristics on page 38 Corrected “CLKL-NOEL” in Section 5.3.10: FSMC characteristics on page 55 Updated Table 48: I2C characteristics on page 78 Corrected note “non-robust “ in Section 5.3.
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STM32F100xC, STM32F100xD, STM32F100xE IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement.