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STM32F072x8 STM32F072xB Functional overview

verifications and ALERT protocol management. I2C1 also has a clock domain independent

from the CPU clock, allowing the I2C1 to wake up the MCU from Stop mode on address

match.

The I2C peripherals can be served by the DMA controller.

Refer to Table 9 for the differences between I2C1 and I2C2.

3.17 Universal synchronous/asynchronous receiver/transmitter

(USART)

The device embeds four universal synchronous/asynchronous receivers/transmitters

(USART1, USART2, USART3, USART4) which communicate at speeds of up to 6

Mbit/s.

They provide hardware management of the CTS, RTS and RS485 DE signals,

multiprocessor communication mode, master synchronous communication and single-wire

half-duplex communication mode. USART1 and USART2 support also SmartCard

communication (ISO 7816), IrDA SIR ENDEC, LIN Master/Slave capability and auto baud

rate feature, and have a clock domain independent of the CPU clock, allowing to wake up

the MCU from Stop mode.

The USART interfaces can be served by the DMA controller.

Table 9. STM32F072x8/xB I

C implementation

C features

(1)

1. X = supported.

I2C1 I2C2

7-bit addressing mode X X

10-bit addressing mode X X

Standard mode (up to 100 kbit/s) X X

Fast mode (up to 400 kbit/s) X X

Fast Mode Plus (up to 1 Mbit/s) with 20 mA output drive I/Os X X

Independent clock X -

SMBus X -

Wakeup from STOP X -

Table 10. STM32F072x8/xB USART implementation

USART modes/features

(1)

USART1 and

USART2

USART3 and

USART4

Hardware flow control for modem X X

Continuous communication using DMA X X

Multiprocessor communication X X

Synchronous mode X X

Smartcard mode X -

Single-wire half-duplex communication X X

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