Datasheet

DocID025451 Rev 6 119/122
STM32F071x8 STM32F071xB Revision history
121
9 Revision history
Table 79. Document revision history
Date Revision Changes
13-Jan-2014 1 Initial draft
21-Feb-2014 2
Added part number STM32F071V8.
Changed status of document from “Preliminary data” to
“Production data”.
Updated “Reset and power management” data in Features.
Updated t
S_vrefint
in Table: Embedded internal reference
voltage.
Updated V
HSEH
and V
HSEL
in Table: High-speed external user
clock characteristics.
Updated V
LSEH
and V
LSEL
in Table: Low-speed external user
clock characteristics.
Updated t
S_temp
in Table: TS characteristics.
Updated t
S_vbat
in Table: VBAT monitoring characteristics.
Updated Section: I
2
C interface characteristics.
Updated Figure: UFBGA100 package top view and Figure:
WLCSP49 package top view.
Modified value of t
s_sc
and removed row V
BG
in Table:
Comparator characteristics.
17-Dec-2015 3
Cover page:
– part numbers moved to title and table of part numbers
removed
– generic product name in the whole document changed to
STM32F071x8/xB
Section 2: Description:
– Figure 1: Block diagram updated
Section 3: Functional overview:
– Figure 2: Clock tree updated
– Section 3.5.4: Low-power modes - added USART2 to
comm. peripherals configurable to operate with HSI
Section 4: Pinouts and pin descriptions:
– Package pinout figures updated (look and feel)
– Figure 8: WLCSP49 package pinout - now presented in
top view
– Figure 3: UFBGA100 package pinout - names of PC14,
PC15, PF0, PF1 complemented
– Table 13: STM32F071x8/xB pin definitions - pin types
corrected for PF0 and PF1
Section 5: Memory mapping:
– Figure 9: added information on STM32F071V8 difference
versus STM32F071xB map
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