Datasheet

ManualsBrandsST ManualsEmbedded Processors & ControllersMicrocontroller 32bit 128KB LQFP

This is information on a product in full production.

January 2017 DocID025451 Rev 6 1/122

STM32F071x8 STM32F071xB

ARM

-based 32-bit MCU, up to 128 KB Flash, 12 timers,

ADC, DAC and communication interfaces, 2.0 - 3.6 V

Datasheet - production data

Features

• Core: ARM

32-bit Cortex

-M0 CPU,

frequency up to 48 MHz

• Memories

– 64 to 128 Kbytes of Flash memory

– 16 Kbytes of SRAM with HW parity

• CRC calculation unit

• Reset and power management

– Digital and I/O supply: V

= 2.0 V to 3.6 V

– Analog supply: V

DDA

= V

to 3.6 V

– Selected I/Os: V

DDIO2

= 1.65 V to 3.6 V

– Power-on/Power down reset (POR/PDR)

– Programmable voltage detector (PVD)

– Low power modes: Sleep, Stop, Standby

–V

BAT

supply for RTC and backup registers

• Clock management

– 4 to 32 MHz crystal oscillator

– 32 kHz oscillator for RTC with calibration

– Internal 8 MHz RC with x6 PLL option

– Internal 40 kHz RC oscillator

– Internal 48 MHz oscillator with automatic

trimming based on ext. synchronization

• Up to 87 fast I/Os

– All mappable on external interrupt vectors

– Up to 68 I/Os with 5V tolerant capability

and 19 with independent supply V

DDIO2

• Seven-channel DMA controller

• One 12-bit, 1.0 µs ADC (up to 16 channels)

– Conversion range: 0 to 3.6 V

– Separate analog supply: 2.4 V to 3.6 V

• One 12-bit D/A converter (with 2 channels)

• Two fast low-power analog comparators with

programmable input and output

• Up to 24 capacitive sensing channels for

touchkey, linear and rotary touch sensors

• Calendar RTC with alarm and periodic wakeup

from Stop/Standby

• 12 timers

– One 16-bit advanced-control timer for

six-channel PWM output

– One 32-bit and seven 16-bit timers, with up

to four IC/OC, OCN, usable for IR control

decoding or DAC control

– Independent and system watchdog timers

– SysTick timer

• Communication interfaces

–Two I

C interfaces supporting Fast Mode

Plus (1 Mbit/s) with 20 mA current sink, one

supporting SMBus/PMBus and wakeup

– Four USARTs supporting master

synchronous SPI and modem control, two

with ISO7816 interface, LIN, IrDA, auto

baud rate detection and wakeup feature

– Two SPIs (18 Mbit/s) with 4 to 16

programmable bit frames, and with I

interface multiplexed

• HDMI CEC, wakeup on header reception

• Serial wire debug (SWD)

• 96-bit unique ID

• All packages ECOPACK

Table 1. Device summary

Reference Part number

STM32F071x8

STM32F071xB

STM32F071C8, STM32F071V8

STM32F071CB, STM32F071RB, STM32F071VB

LQFP100 14x14 mm

LQFP64 10x10 mm

LQFP48 7x7 mm

UFQFPN48

7x7 mm

UFBGA100

)%*$

7x7 mm

WLCSP49

3.3x3.1 mm

www.st.com

Downloaded from Arrow.com.

Summary of content (122 pages)

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STM32F071x8 STM32F071xB ARM®-based 32-bit MCU, up to 128 KB Flash, 12 timers, ADC, DAC and communication interfaces, 2.0 - 3.6 V Datasheet - production data Features )%*$ ® ® • Core: ARM 32-bit Cortex -M0 CPU, frequency up to 48 MHz LQFP100 14x14 mm UFQFPN48 LQFP64 10x10 mm 7x7 mm LQFP48 7x7 mm • Memories – 64 to 128 Kbytes of Flash memory – 16 Kbytes of SRAM with HW parity UFBGA100 7x7 mm WLCSP49 3.3x3.
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Contents STM32F071x8 STM32F071xB Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3 Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.1 ARM®-Cortex®-M0 core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.2 Memories . . . . . .
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STM32F071x8 STM32F071xB 3.14.6 Contents SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.15 Real-time clock (RTC) and backup registers . . . . . . . . . . . . . . . . . . . . . . 23 3.16 Inter-integrated circuit interface (I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.17 Universal synchronous/asynchronous receiver/transmitter (USART) . . . 25 3.
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Contents 7 STM32F071x8 STM32F071xB 6.3.12 Electrical sensitivity characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 6.3.13 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 6.3.14 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 6.3.15 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 6.3.16 12-bit ADC characteristics . . .
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STM32F071x8 STM32F071xB List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. Table 43. Table 44. Table 45. Table 46.
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List of tables Table 47. Table 48. Table 49. Table 50. Table 51. Table 52. Table 53. Table 54. Table 55. Table 56. Table 57. Table 58. Table 59. Table 60. Table 61. Table 62. Table 63. Table 64. Table 65. Table 66. Table 67. Table 68. Table 69. Table 70. Table 71. Table 72. Table 73. Table 74. Table 75. Table 76. Table 77. Table 78. Table 79. 6/122 Downloaded from Arrow.com. STM32F071x8 STM32F071xB Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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STM32F071x8 STM32F071xB List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Figure 38. Figure 39. Figure 40. Figure 41. Figure 42.
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List of figures Figure 49. Figure 50. Figure 51. 8/122 Downloaded from Arrow.com. STM32F071x8 STM32F071xB Recommended footprint for UFQFPN48 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 UFQFPN48 package marking example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 LQFP64 PD max versus TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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STM32F071x8 STM32F071xB 1 Introduction Introduction This datasheet provides the ordering information and mechanical device characteristics of the STM32F071x8/xB microcontrollers. This document should be read in conjunction with the STM32F0xxxx reference manual (RM0091). The reference manual is available from the STMicroelectronics website www.st.com. For information on the ARM® Cortex®-M0 core, please refer to the Cortex®-M0 Technical Reference Manual, available from the www.arm.com website.
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Description 2 STM32F071x8 STM32F071xB Description The STM32F071x8/xB microcontrollers incorporate the high-performance ARM® Cortex®M0 32-bit RISC core operating at up to 48 MHz frequency, high-speed embedded memories (up to 128 Kbytes of Flash memory and 16 Kbytes of SRAM), and an extensive range of enhanced peripherals and I/Os.
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STM32F071x8 STM32F071xB Description Table 2. STM32F071x8/xB family device features and peripheral counts Peripheral STM32F071Cx Flash memory (Kbyte) 64 STM32F071RB 128 128 SRAM (Kbyte) Timers Comm. interfaces 1 (16-bit) General purpose 5 (16-bit) 1 (32-bit) Basic 2 (16-bit) SPI [I2S](1) 2 [2] 2C 2 USART 4 CEC 1 12-bit ADC (number of channels) 64 128 16 Advanced control I STM32F071Vx 1 (10 ext. + 3 int.) 1 (16 ext. + 3 int.
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Description STM32F071x8 STM32F071xB Figure 1. Block diagram 32:(5 6HULDO :LUH 'HEXJ 2EO )ODVK PHPRU\ LQWHUIDFH 6:&/. 6:',2 DV $) 65$0 FRQWUROOHU 19,& %XV PDWUL[ &257(; 0 &38 I0$; 0+] 92/7 5(* 9 WR 9 9'' )ODVK *3/ XS WR .% ELW # 9'' 65$0 .% # 9''$ +6, +6, 3//&/. /6, *3 '0$ FKDQQHOV +6, 9'' WR 9 966 9'',2 2.
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STM32F071x8 STM32F071xB 3 Functional overview Functional overview Figure 1 shows the general block diagram of the STM32F071x8/xB devices. 3.1 ARM®-Cortex®-M0 core The ARM® Cortex®-M0 is a generation of ARM 32-bit RISC processors for embedded systems. It has been developed to provide a low-cost platform that meets the needs of MCU implementation, with a reduced pin count and low-power consumption, while delivering outstanding computational performance and an advanced system response to interrupts.
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Functional overview 3.4 STM32F071x8 STM32F071xB Cyclic redundancy check calculation unit (CRC) The CRC (cyclic redundancy check) calculation unit is used to get a CRC code using a configurable generator polynomial value and size. Among other applications, CRC-based techniques are used to verify data transmission or storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of verifying the Flash memory integrity.
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STM32F071x8 STM32F071xB Functional overview threshold. The interrupt service routine can then generate a warning message and/or put the MCU into a safe state. The PVD is enabled by software. 3.5.3 Voltage regulator The regulator has two operating modes and it is always enabled after reset. • Main (MR) is used in normal operating mode (Run). • Low power (LPR) can be used in Stop mode where the power demand is reduced. In Standby mode, it is put in power down mode.
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Functional overview STM32F071x8 STM32F071xB back to the internal RC oscillator. A software interrupt is generated if enabled. Similarly, full interrupt management of the PLL clock entry is available when necessary (for example on failure of an indirectly used external crystal, resonator or oscillator). Figure 2. Clock tree 6<1& )/,7)&/. /6( 6<1&65& , & 6: )ODVK PHPRU\ SURJUDPPLQJ LQWHUIDFH +6, &56 , & 6<6&/.
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STM32F071x8 STM32F071xB Functional overview Additionally, also the internal RC 48 MHz oscillator can be selected for system clock or PLL input source. This oscillator can be automatically fine-trimmed by the means of the CRS peripheral using the external synchronization. 3.7 General-purpose inputs/outputs (GPIOs) Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as input (with or without pull-up or pull-down) or as peripheral alternate function.
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Functional overview 3.9.2 STM32F071x8 STM32F071xB Extended interrupt/event controller (EXTI) The extended interrupt/event controller consists of 32 edge detector lines used to generate interrupt/event requests and wake-up the system. Each line can be independently configured to select the trigger event (rising edge, falling edge, both) and can be masked independently. A pending register maintains the status of the interrupt requests.
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STM32F071x8 STM32F071xB Functional overview precise voltage of VREFINT is individually measured for each part by ST during production test and stored in the system memory area. It is accessible in read-only mode. Table 4. Internal voltage reference calibration values 3.10.3 Calibration value name Description Memory address VREFINT_CAL Raw data acquired at a temperature of 30 °C (± 5 °C), VDDA= 3.
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Functional overview STM32F071x8 STM32F071xB Both comparators can wake up from STOP mode, generate interrupts and breaks for the timers and can be also combined into a window comparator. 3.13 Touch sensing controller (TSC) The STM32F071x8/xB devices provide a simple solution for adding capacitive sensing functionality to any application. These devices offer up to 24 capacitive sensing channels distributed over 8 analog I/O groups.
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STM32F071x8 STM32F071xB Functional overview Table 6. Number of capacitive sensing channels available on STM32F071x8/xB devices Number of capacitive sensing channels Analog I/O group 3.
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Functional overview 3.14.1 STM32F071x8 STM32F071xB Advanced-control timer (TIM1) The advanced-control timer (TIM1) can be seen as a three-phase PWM multiplexed on six channels. It has complementary PWM outputs with programmable inserted dead times. It can also be seen as a complete general-purpose timer.
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STM32F071x8 STM32F071xB Functional overview TIM15 has two independent channels, whereas TIM16 and TIM17 feature one single channel for input capture/output compare, PWM or one-pulse mode output. The TIM15, TIM16 and TIM17 timers can work together, and TIM15 can also operate withTIM1 via the Timer Link feature for synchronization or event chaining. TIM15 can be synchronized with TIM16 and TIM17.
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Functional overview STM32F071x8 STM32F071xB The RTC is an independent BCD timer/counter. Its main features are the following: • calendar with subseconds, seconds, minutes, hours (12 or 24 format), week day, date, month, year, in BCD (binary-coded decimal) format • automatic correction for 28, 29 (leap year), 30, and 31 day of the month • programmable alarm with wake up from Stop and Standby mode capability • Periodic wakeup unit with programmable resolution and period.
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STM32F071x8 STM32F071xB Functional overview verifications and ALERT protocol management. I2C1 also has a clock domain independent from the CPU clock, allowing the I2C1 to wake up the MCU from Stop mode on address match. The I2C peripherals can be served by the DMA controller. Refer to Table 9 for the differences between I2C1 and I2C2. Table 9.
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Functional overview STM32F071x8 STM32F071xB Table 10. STM32F071x8/xB USART implementation (continued) USART1 and USART2 USART3 and USART4 IrDA SIR ENDEC block X - LIN mode X - Dual clock domain and wakeup from Stop mode X - Receiver timeout interrupt X - Modbus communication X - Auto baud rate detection X - Driver Enable X X USART modes/features(1) 1. X = supported. 3.
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STM32F071x8 STM32F071xB Functional overview overhead. It has a clock domain independent from the CPU clock, allowing the HDMI_CEC controller to wakeup the MCU from Stop mode on data reception. 3.20 Clock recovery system (CRS) The STM32F071x8/xB embeds a special block which allows automatic trimming of the internal 48 MHz oscillator to guarantee its optimal accuracy over the whole device operational range.
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Pinouts and pin descriptions 4 STM32F071x8 STM32F071xB Pinouts and pin descriptions Figure 3.
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STM32F071x8 STM32F071xB Pinouts and pin descriptions /4)3 9'',2 966 3) 3$ 3$ 3$ 3$ 3$ 3$ 3& 3& 3& 3& 3' 3' 3' 3' 3' 3' 3' 3' 3% 3% 3% 3% 3$ 966 9'' 3$ 3$ 3$ 3$ 3& 3& 3% 3% 3% 3( 3( 3( 3( 3( 3( 3( 3( 3( 3% 3% 966
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Pinouts and pin descriptions STM32F071x8 STM32F071xB /4)3 9'',2 966 3$ 3$ 3$ 3$ 3$ 3$ 3& 3& 3& 3& 3% 3% 3% 3% 3$ 966 9'' 3$ 3$ 3$ 3$ 3& 3& 3% 3% 3% 3% 3% 966 9'' 9%$7 3& 3& 26& B,1 3& 26& B287 3) 26&B,1 3) 26&B287 1567 3& 3&
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STM32F071x8 STM32F071xB Pinouts and pin descriptions Figure 7.
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Pinouts and pin descriptions STM32F071x8 STM32F071xB Table 12. Legend/abbreviations used in the pinout table Name Abbreviation Unless otherwise specified in brackets below the pin name, the pin function during and after reset is the same as the actual pin name Pin name Pin type I/O structure S Supply pin I Input-only pin I/O Input / output pin FT 5 V-tolerant I/O FTf 5 V-tolerant I/O, FM+ capable TTa 3.3 V-tolerant I/O directly connected to ADC TC Standard 3.
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STM32F071x8 STM32F071xB Pinouts and pin descriptions Table 13.
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Pinouts and pin descriptions STM32F071x8 STM32F071xB Table 13.
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STM32F071x8 STM32F071xB Pinouts and pin descriptions Table 13.
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Pinouts and pin descriptions STM32F071x8 STM32F071xB Table 13.
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STM32F071x8 STM32F071xB Pinouts and pin descriptions Table 13.
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Pinouts and pin descriptions STM32F071x8 STM32F071xB Table 13.
PAGE 39
AF0 - EVENTOUT TIM15_CH1 TIM15_CH2 SPI1_NSS, I2S1_WS SPI1_SCK, I2S1_CK SPI1_MISO, I2S1_MCK SPI1_MOSI, I2S1_SD MCO TIM15_BKIN TIM17_BKIN EVENTOUT EVENTOUT SWDIO SWCLK SPI1_NSS, I2S1_WS Pin name PA0 Downloaded from Arrow.com.
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AF0 EVENTOUT TIM14_CH1 - SPI1_SCK, I2S1_CK SPI1_MISO, I2S1_MCK SPI1_MOSI, I2S1_SD USART1_TX USART1_RX CEC IR_OUT CEC EVENTOUT SPI2_NSS, I2S2_WS SPI2_SCK, I2S2_CK SPI2_MISO, I2S2_MCK SPI2_MOSI, I2S2_SD Pin name PB0 40/122 Downloaded from Arrow.com.
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STM32F071x8 STM32F071xB Table 16. Alternate functions selected through GPIOC_AFR registers for port C Pin name AF0 AF1 PC0 EVENTOUT - PC1 EVENTOUT - PC2 EVENTOUT SPI2_MISO, I2S2_MCK PC3 EVENTOUT SPI2_MOSI, I2S2_SD PC4 EVENTOUT USART3_TX PC5 TSC_G3_IO1 USART3_RX PC6 TIM3_CH1 - PC7 TIM3_CH2 - PC8 TIM3_CH3 - PC9 TIM3_CH4 - PC10 USART4_TX USART3_TX PC11 USART4_RX USART3_RX PC12 USART4_CK USART3_CK PC13 - - PC14 - - PC15 - - Table 17.
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STM32F071x8 STM32F071xB Table 18.
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STM32F071x8 STM32F071xB 5 Memory mapping Memory mapping To the difference of STM32F071xB memory map in Figure 9, the two bottom code memory spaces of STM32F071x8 end at 0x0000 FFFF and 0x0800 FFFF, respectively. Figure 9.
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Memory mapping STM32F071x8 STM32F071xB Table 20. STM32F071x8/xB peripheral register boundary addresses Bus AHB2 AHB1 APB 44/122 Downloaded from Arrow.com.
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STM32F071x8 STM32F071xB Memory mapping Table 20.
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Electrical characteristics STM32F071x8 STM32F071xB 6 Electrical characteristics 6.1 Parameter conditions Unless otherwise specified, all voltages are referenced to VSS. 6.1.1 Minimum and maximum values Unless otherwise specified, the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at TA = 25 °C and TA = TAmax (given by the selected temperature range).
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STM32F071x8 STM32F071xB 6.1.6 Electrical characteristics Power supply scheme Figure 12. Power supply scheme 9%$7 %DFNXS FLUFXLWU\ /6( 57& %DFNXS UHJLVWHUV ± 9 3RZHU VZLWFK 9'' 9&25( [ 9'' 5HJXODWRU [ Q) *3,2V ,1 [ ) /HYHO VKLIWHU 287 ,2 ORJLF /HYHO VKLIWHU 9'',2 ,2 ORJLF .
PAGE 48
Electrical characteristics 6.1.7 STM32F071x8 STM32F071xB Current consumption measurement Figure 13. Current consumption measurement scheme , ''B9%$7 9 %$7 , '' 9 '' 9 '',2 , ''$ 9 ''$ 06 9 48/122 Downloaded from Arrow.com.
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STM32F071x8 STM32F071xB 6.2 Electrical characteristics Absolute maximum ratings Stresses above the absolute maximum ratings listed in Table 21: Voltage characteristics, Table 22: Current characteristics and Table 23: Thermal characteristics may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Table 21.
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Electrical characteristics STM32F071x8 STM32F071xB Table 22. Current characteristics Symbol Ratings Max.
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STM32F071x8 STM32F071xB Electrical characteristics 6.3 Operating conditions 6.3.1 General operating conditions Table 24. General operating conditions Symbol Parameter Conditions Min Max Unit fHCLK Internal AHB clock frequency - 0 48 fPCLK Internal APB clock frequency - 0 48 VDD Standard operating voltage - 2.0 3.6 V Must not be supplied if VDD is not present 1.65 3.6 V VDD 3.6 2.4 3.6 1.65 3.6 TC and RST I/O –0.3 VDDIOx+0.3 TTa I/O –0.3 VDDA+0.
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Electrical characteristics STM32F071x8 STM32F071xB Table 25. Operating conditions at power-up / power-down Symbol Parameter VDD rise time rate tVDD - VDD fall time rate VDDA rise time rate tVDDA 6.3.
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STM32F071x8 STM32F071xB Electrical characteristics Table 27. Programmable voltage detector characteristics (continued) Symbol Parameter Conditions Min Typ Max Unit Rising edge 2.66 2.78 2.9 V Falling edge 2.56 2.68 2.8 V Rising edge 2.76 2.88 3 V Falling edge 2.66 2.78 2.9 V VPVD6 PVD threshold 6 VPVD7 PVD threshold 7 VPVDhyst(1) PVD hysteresis - - 100 - mV PVD current consumption - - 0.15 0.26(1) µA IDD(PVD) 1. Guaranteed by design, not tested in production.
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Electrical characteristics STM32F071x8 STM32F071xB Typical and maximum current consumption The MCU is placed under the following conditions: • All I/O pins are in analog input mode • All peripherals are disabled except when explicitly mentioned • • The Flash memory access time is adjusted to the fHCLK frequency: – 0 wait state and Prefetch OFF from 0 to 24 MHz – 1 wait state and Prefetch ON above 24 MHz When the peripherals are enabled fPCLK = fHCLK The parameters given in to Table 31 are deriv
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STM32F071x8 STM32F071xB Electrical characteristics Symbol Parameter Table 29. Typical and maximum current consumption from VDD supply at VDD = 3.6 V (continued) All peripherals enabled Conditions Supply current in Run mode, code executing from RAM Supply current in Sleep mode IDD Max @ TA(1) fHCLK Max @ TA(1) 48 MHz 23.1 Unit Typ Typ HSI48 All peripherals disabled 25 °C 85 °C 105 °C 25.4 25.8 26.6 25.7 26.5(2) 85 °C 105 °C 12.8 13.5 13.7 13.9 12.6 13.3(2) 13.5 13.
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Electrical characteristics STM32F071x8 STM32F071xB Table 30. Typical and maximum current consumption from the VDDA supply VDDA = 2.4 V Symbol Parameter Conditions (1) IDDA Max @ TA(2) fHCLK Max @ TA(2) HSE bypass, PLL on HSE bypass, PLL off HSI clock, PLL on HSI clock, PLL off 48 MHz 311 Unit Typ Typ HSI48 Supply current in Run or Sleep mode, code executing from Flash memory or RAM VDDA = 3.
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STM32F071x8 STM32F071xB Electrical characteristics Table 31. Typical and maximum consumption in Stop and Standby modes Max(1) Typ @VDD (VDD = VDDA) Parameter Supply current in Stop mode IDD Supply current in Standby mode Supply current in Stop mode Supply current in Standby mode Conditions 2.0 V 2.4 V 2.7 V 3.0 V 3.3 V 3.6 V TA = 25 °C TA = 85 °C TA = 105 °C Regulator in run mode, all oscillators OFF 15.4 15.5 15.6 15.7 15.8 15.
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Electrical characteristics STM32F071x8 STM32F071xB Table 32. Typical and maximum current consumption from the VBAT supply Max(1) Typ @ VBAT 2.4 V 2.7 V 3.3 V 3.6 V RTC domain IDD_VBAT supply current Conditions 1.8 V Parameter 1.65 V Symbol TA = 25 °C LSE & RTC ON; “Xtal mode”: lower driving capability; LSEDRV[1:0] = '00' 0.5 0.6 0.7 0.8 1.1 1.2 1.3 LSE & RTC ON; “Xtal mode” higher driving capability; LSEDRV[1:0] = '11' 0.8 TA = TA = 85 °C 105 °C 1.7 Unit 2.3 µA 0.9 1.1 1.2 1.
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STM32F071x8 STM32F071xB Electrical characteristics Table 33. Typical current consumption, code executing from Flash memory, running from HSE 8 MHz crystal Typical consumption in Run mode Symbol Parameter Typical consumption in Sleep mode fHCLK Unit Peripherals Peripherals Peripherals Peripherals enabled disabled enabled disabled IDD IDDA Current consumption from VDD supply Current consumption from VDDA supply 48 MHz 23.5 13.5 14.6 3.5 36 MHz 18.3 10.5 11.1 2.9 32 MHz 16.0 9.6 10.
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Electrical characteristics STM32F071x8 STM32F071xB trigger circuits used to discriminate the input value. Unless this specific configuration is required by the application, this supply current consumption can be avoided by configuring these I/Os in analog mode. This is notably the case of ADC input pins which should be configured as analog inputs. Caution: Any floating input pin can also settle to an intermediate voltage level or switch inadvertently, as a result of external electromagnetic noise.
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STM32F071x8 STM32F071xB Electrical characteristics Table 34. Switching output I/O current consumption Symbol Parameter Conditions(1) VDDIOx = 3.3 V C =CINT VDDIOx = 3.3 V CEXT = 0 pF C = CINT + CEXT+ CS VDDIOx = 3.3 V CEXT = 10 pF C = CINT + CEXT+ CS ISW I/O current consumption VDDIOx = 3.3 V CEXT = 22 pF C = CINT + CEXT+ CS VDDIOx = 3.3 V CEXT = 33 pF C = CINT + CEXT+ CS VDDIOx = 3.3 V CEXT = 47 pF C = CINT + CEXT+ CS C = Cint VDDIOx = 2.
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Electrical characteristics STM32F071x8 STM32F071xB On-chip peripheral current consumption The current consumption of the on-chip peripherals is given in Table 35.
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STM32F071x8 STM32F071xB Electrical characteristics Table 35. Peripheral current consumption (continued) Peripheral APB-Bridge Typical consumption at 25 °C (2) 2.8 ADC(3) 4.1 CEC 1.5 CRS 0.8 (3) APB Unit DAC 4.7 DEBUG (MCU debug feature) 0.1 I2C1 3.9 I2C2 4.0 PWR 1.3 SPI1 8.7 SPI2 8.5 SYSCFG & COMP 1.7 TIM1 14.9 TIM2 15.5 TIM3 11.4 TIM6 2.5 TIM7 2.3 TIM14 5.3 TIM15 9.1 TIM16 6.6 TIM17 6.8 USART1 17.0 USART2 16.7 USART3 5.4 USART4 5.4 WWDG 1.
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Electrical characteristics 6.3.6 STM32F071x8 STM32F071xB Wakeup time from low-power mode The wakeup times given in Table 36 are the latency between the event and the execution of the first user instruction. The device goes in low-power mode after the WFE (Wait For Event) instruction, in the case of a WFI (Wait For Interruption) instruction, 16 CPU cycles must be added to the following timings due to the interrupt latency in the Cortex M0 architecture.
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STM32F071x8 STM32F071xB Electrical characteristics 1. Guaranteed by design, not tested in production. Figure 14. High-speed external clock source AC timing diagram WZ +6(+ 9+6(+ 9+6(/ WU +6( WI +6( W WZ +6(/ 7+6( 06 9 Low-speed external user clock generated from an external source In bypass mode the LSE oscillator is switched off and the input pin is a standard GPIO. The external clock signal has to respect the I/O characteristics in Section 6.3.14.
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Electrical characteristics STM32F071x8 STM32F071xB High-speed external clock generated from a crystal/ceramic resonator The high-speed external (HSE) clock can be supplied with a 4 to 32 MHz crystal/ceramic resonator oscillator. All the information given in this paragraph are based on design simulation results obtained with typical external components specified in Table 39.
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STM32F071x8 STM32F071xB Electrical characteristics Figure 16. Typical application with an 8 MHz crystal 5HVRQDWRU ZLWK LQWHJUDWHG FDSDFLWRUV &/ 26&B,1 0+] UHVRQDWRU &/ 5(;7 I+6( 5) %LDV FRQWUROOHG JDLQ 26&B287 06 9 1. REXT value depends on the crystal characteristics. Low-speed external clock generated from a crystal resonator The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal resonator oscillator.
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Electrical characteristics Note: STM32F071x8 STM32F071xB For information on selecting the crystal, refer to the application note AN2867 “Oscillator design guide for ST microcontrollers” available from the ST website www.st.com. Figure 17. Typical application with a 32.
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STM32F071x8 STM32F071xB Electrical characteristics High-speed internal (HSI) RC oscillator Table 41. HSI oscillator characteristics(1) Symbol Parameter fHSI Conditions Min Typ - - Frequency TRIM HSI user trimming step DuCy(HSI) Duty cycle Accuracy of the HSI oscillator ACCHSI - - - (2) 45 IDDA(HSI) Unit 8 - MHz - (2) - % 1 (2) 55 % TA = -40 to 105°C (3) -2.8 - 3.8 TA = -10 to 85°C -1.9(3) - 2.3(3) TA = 0 to 85°C -1.9(3) - 2(3) TA = 0 to 70°C -1.
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Electrical characteristics STM32F071x8 STM32F071xB High-speed internal 14 MHz (HSI14) RC oscillator (dedicated to ADC) Table 42. HSI14 oscillator characteristics(1) Symbol fHSI14 TRIM Parameter Conditions Min Typ - - 14 Frequency HSI14 user-trimming step DuCy(HSI14) Duty cycle - - - (2) 45 Accuracy of the HSI14 oscillator (factory calibrated) TA = –10 to 85 °C TA = 25 °C tsu(HSI14) IDDA(HSI14) - MHz (2) - % 1 55 (2) % (3) % (3) - 5.1 –3.2(3) - 3.1(3) % –2.5 - 2.
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STM32F071x8 STM32F071xB Electrical characteristics High-speed internal 48 MHz (HSI48) RC oscillator Table 43. HSI48 oscillator characteristics(1) Symbol fHSI48 TRIM Parameter Conditions Min Typ Max Unit - - 48 - MHz Frequency HSI48 user-trimming step (2) - DuCy(HSI48) Duty cycle 0.09 - 45 TA = –40 to 105 °C ACCHSI48 TA = –10 to 85 °C Accuracy of the HSI48 oscillator (factory calibrated) T = 0 to 70 °C A IDDA(HSI48) 0.14 - % (2) % (3) 0.2 55 (3) - 4.7 % -4.1(3) - 3.
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Electrical characteristics STM32F071x8 STM32F071xB Low-speed internal (LSI) RC oscillator Table 44. LSI oscillator characteristics(1) Symbol Parameter fLSI tsu(LSI) Min Typ Max Unit 30 40 50 kHz LSI oscillator startup time - - 85 µs LSI oscillator power consumption - 0.75 1.2 µA Frequency (2) IDDA(LSI)(2) 1. VDDA = 3.3 V, TA = –40 to 105 °C unless otherwise specified. 2. Guaranteed by design, not tested in production. 6.3.
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STM32F071x8 STM32F071xB Electrical characteristics Table 47. Flash memory endurance and data retention Symbol NEND Parameter Endurance Conditions TA = –40 to +105 °C 1 tRET Data retention kcycle(2) Min(1) Unit 10 kcycle at TA = 85 °C 30 at TA = 105 °C 10 10 kcycle(2) at TA = 55 °C 20 1 kcycle (2) Year 1. Data based on characterization results, not tested in production. 2. Cycling performed over the whole temperature range. 6.3.
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Electrical characteristics STM32F071x8 STM32F071xB Software recommendations The software flowchart must include the management of runaway conditions such as: • Corrupted program counter • Unexpected reset • Critical Data corruption (for example control registers) Prequalification trials Most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1 second.
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STM32F071x8 STM32F071xB Electrical characteristics Table 50. ESD absolute maximum ratings Symbol Ratings Conditions Packages Class Maximum value(1) Unit All 2 2000 V C3 250 C4 500 VESD(HBM) Electrostatic discharge voltage TA = +25 °C, conforming (human body model) to JESD22-A114 VESD(CDM) Electrostatic discharge voltage TA = +25 °C, conforming WLCSP49 (charge device model) to ANSI/ESD STM5.3.1 All others V 1. Data based on characterization results, not tested in production.
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Electrical characteristics STM32F071x8 STM32F071xB Table 52. I/O current injection susceptibility Functional susceptibility Symbol Description Unit Negative Positive injection injection IINJ 6.3.
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STM32F071x8 STM32F071xB Electrical characteristics Table 53. I/O static characteristics (continued) Symbol Ilkg RPU Parameter Input leakage current(2) Weak pull-up equivalent resistor (3) RPD Weak pull-down equivalent resistor(3) CIO I/O pin capacitance Conditions Min Typ Max TC, FT and FTf I/O TTa in digital mode VSS ≤ VIN ≤ VDDIOx - - ± 0.1 TTa in digital mode VDDIOx ≤ VIN ≤ VDDA - - 1 TTa in analog mode VSS ≤ VIN ≤ VDDA - - ± 0.
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Electrical characteristics STM32F071x8 STM32F071xB Figure 21.
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STM32F071x8 STM32F071xB Electrical characteristics Output driving current The GPIOs (general purpose input/outputs) can sink or source up to +/-8 mA, and sink or source up to +/- 20 mA (with a relaxed VOL/VOH). In the user application, the number of I/O pins which can drive current must be limited to respect the absolute maximum rating specified in Section 6.
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Electrical characteristics STM32F071x8 STM32F071xB Input/output AC characteristics The definition and values of input/output AC characteristics are given in Figure 23 and Table 55, respectively. Unless otherwise specified, the parameters given are derived from tests performed under the ambient temperature and supply voltage conditions summarized in Table 24: General operating conditions. Table 55.
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STM32F071x8 STM32F071xB Electrical characteristics Table 55.
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Electrical characteristics STM32F071x8 STM32F071xB Table 56. NRST pin characteristics (continued) Symbol Parameter Conditions Min Typ Max Unit Vhys(NRST) NRST Schmitt trigger voltage hysteresis - - 200 - mV RPU Weak pull-up equivalent resistor(2) VIN = VSS 25 40 55 kΩ VF(NRST) NRST input filtered pulse - - - 100(1) ns 2.7 < VDD < 3.6 300(3) - - 2.0 < VDD < 3.6 (3) - - VNF(NRST) NRST input not filtered pulse 500 ns 1. Data based on design simulation only.
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STM32F071x8 STM32F071xB Electrical characteristics Table 57.
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Electrical characteristics STM32F071x8 STM32F071xB Equation 1: RAIN max formula TS - – R ADC R AIN < --------------------------------------------------------------N+2 f ADC × C ADC × ln ( 2 ) The formula above (Equation 1) is used to determine the maximum external impedance allowed for an error below 1/4 of LSB. Here N = 12 (from 12-bit resolution). Table 58. RAIN max for fADC = 14 MHz Ts (cycles) tS (µs) RAIN max (kΩ)(1) 1.5 0.11 0.4 7.5 0.54 5.9 13.5 0.96 11.4 28.5 2.04 25.2 41.5 2.
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STM32F071x8 STM32F071xB Electrical characteristics 2. ADC Accuracy vs. Negative Injection Current: Injecting negative current on any of the standard (non-robust) analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a Schottky diode (pin to ground) to standard analog pins which may potentially inject negative current.
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Electrical characteristics 6.3.17 STM32F071x8 STM32F071xB DAC electrical specifications Table 60. DAC characteristics Symbol Parameter VDDA Analog supply voltage for DAC ON RLOAD(1) Resistive load with buffer ON RO(1) CLOAD(1) Min Typ Max Unit Comments 2.4 - 3.
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STM32F071x8 STM32F071xB Electrical characteristics Table 60. DAC characteristics (continued) Symbol Min Typ Max Unit Gain error(3) Gain error - - ±0.
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Electrical characteristics 6.3.18 STM32F071x8 STM32F071xB Comparator characteristics Table 61. Comparator characteristics Symbol Parameter Conditions Min(1) Typ Max(1) Unit Analog supply voltage - VDD - 3.6 V VIN Comparator input voltage range - 0 - VDDA - VSC VREFINT scaler offset voltage - - ±5 ±10 mV tS_SC VREFINT scaler startup time from power down First VREFINT scaler activation after device power on - - Next activations - - 0.
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STM32F071x8 STM32F071xB Electrical characteristics Table 61.
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Electrical characteristics 6.3.19 STM32F071x8 STM32F071xB Temperature sensor characteristics Table 62. TS characteristics Symbol Parameter TL(1) Avg_Slope Min Typ Max Unit - ±1 ±2 °C 4.0 4.3 4.6 mV/°C 1.34 1.43 1.52 V VSENSE linearity with temperature (1) V30 Average slope (2) Voltage at 30 °C (± 5 °C) tSTART(1) ADC_IN16 buffer startup time - - 10 µs tS_temp(1) ADC sampling time when reading the temperature 4 - - µs 1. Guaranteed by design, not tested in production. 2.
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STM32F071x8 STM32F071xB Electrical characteristics Table 65. IWDG min/max timeout period at 40 kHz (LSI)(1) Prescaler divider PR[2:0] bits Min timeout RL[11:0]= 0x000 Max timeout RL[11:0]= 0xFFF /4 0 0.1 409.6 /8 1 0.2 819.2 /16 2 0.4 1638.4 /32 3 0.8 3276.8 /64 4 1.6 6553.6 /128 5 3.2 13107.2 /256 6 or 7 6.4 26214.4 Unit ms 1. These timings are given for a 40 kHz clock but the microcontroller internal RC frequency can vary from 30 to 60 kHz.
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Electrical characteristics STM32F071x8 STM32F071xB Table 67. I2C analog filter characteristics(1) Symbol tAF Parameter Maximum width of spikes that are suppressed by the analog filter Min Max Unit 50(2) 260(3) ns 1. Guaranteed by design, not tested in production. 2. Spikes with widths below tAF(min) are filtered. 3.
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STM32F071x8 STM32F071xB Electrical characteristics Figure 29. SPI timing diagram - slave mode and CPHA = 0 166 LQSXW WF 6&. 6&. LQSXW WVX 166 WK 166 WZ 6&.+ WU 6&. &3+$ &32/ &3+$ &32/ WD 62 WZ 6&./ 0,62 RXWSXW WY 62 WK 62 )LUVW ELW 287 WI 6&. 1H[W ELWV 287 WGLV 62 /DVW ELW 287 WK 6, WVX 6, 026, LQSXW )LUVW ELW ,1 1H[W ELWV ,1 /DVW ELW ,1 06Y 9 Figure 30. SPI timing diagram - slave mode and CPHA = 1 166 LQSXW 6&. LQSXW WF 6&. WVX 166 WZ 6&.+ WD 62 WZ 6&./ WI 6&.
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Electrical characteristics STM32F071x8 STM32F071xB Figure 31. SPI timing diagram - master mode +LJK 166 LQSXW 6&. 2XWSXW &3+$ &32/ 6&. 2XWSXW WF 6&. &3+$ &32/ &3+$ &32/ &3+$ &32/ WZ 6&.+ WZ 6&./ WVX 0, 0,62 ,13 87 WU 6&. WI 6&. %,7 ,1 06% ,1 /6% ,1 WK 0, 026, 287387 % , 7 287 06% 287 WY 02 /6% 287 WK 02 DL F 1. Measurement points are done at CMOS levels: 0.3 VDD and 0.7 VDD. Table 69.
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STM32F071x8 STM32F071xB Electrical characteristics Table 69. I2S characteristics(1) (continued) Symbol tsu(SD_MR) tsu(SD_SR) th(SD_MR) th(SD_SR) Parameter Data input setup time (2) (2) tv(SD_MT)(2) tv(SD_ST)(2) th(SD_MT) th(SD_ST) Data input hold time Data output valid time Data output hold time Conditions Min Max Master receiver 6 - Slave receiver 2 - Master receiver 4 - Slave receiver 0.
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Electrical characteristics STM32F071x8 STM32F071xB Figure 33. I2S master timing diagram (Philips protocol) WI &. WU &. &. RXWSXW WF &. &32/ WZ &.+ &32/ WY :6 WK :6 WZ &./ :6 RXWSXW WY 6'B07 6'WUDQVPLW /6% WUDQVPLW 06% WUDQVPLW /6% UHFHLYH /6% WUDQVPLW WK 6'B05 WVX 6'B05 6'UHFHLYH %LWQ WUDQVPLW WK 6'B07 06% UHFHLYH %LWQ UHFHLYH /6% UHFHLYH 06Y 9 1. Data based on characterization results, not tested in production. 2.
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STM32F071x8 STM32F071xB 7 Package information Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. 7.1 UFBGA100 package information UFBGA100 is a 100-ball, 7 x 7 mm, 0.50 mm pitch, ultra-fine-profile ball grid array package. Figure 34.
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Package information STM32F071x8 STM32F071xB Table 70. UFBGA100 package mechanical data (continued) inches(1) millimeters Symbol Min. Typ. Max. Min. Typ. Max. b 0.240 0.290 0.340 0.0094 0.0114 0.0134 D 6.850 7.000 7.150 0.2697 0.2756 0.2815 D1 - 5.500 - - 0.2165 - E 6.850 7.000 7.150 0.2697 0.2756 0.2815 E1 - 5.500 - - 0.2165 - e - 0.500 - - 0.0197 - Z - 0.750 - - 0.0295 - ddd - - 0.080 - - 0.0031 eee - - 0.150 - - 0.0059 fff - - 0.
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STM32F071x8 STM32F071xB Package information Device marking The following figure gives an example of topside marking orientation versus pin 1 identifier location. Other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below. Figure 36. UFBGA100 package marking example WƌŽĚƵĐƚ ŝĚĞŶƚŝĨŝĐĂƚŝŽŶ ;ϭͿ 670 ) 9%+ ĂƚĞ ĐŽĚĞ < :: WŝŶ ϭ ŝĚĞŶƚŝĨŝĞƌ ZĞǀŝƐŝŽŶ ĐŽĚĞ 5 D^ϯϵϬϭϬsϭ 1.
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Package information 7.2 STM32F071x8 STM32F071xB LQFP100 package information LQFP100 is a100-pin, 14 x 14 mm low-profile quad flat package. Figure 37. LQFP100 package outline PP F $ $ $ 6($7,1* 3/$1( & *$8*( 3/$1( ' $ . FFF & / ' / ' 3,1 ,'(17,),&$7,21 ( ( ( E H /B0(B9 1. Drawing is not to scale. Table 72. LQPF100 package mechanical data inches(1) millimeters Symbol 100/122 Downloaded from Arrow.com.
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STM32F071x8 STM32F071xB Package information Table 72. LQPF100 package mechanical data (continued) inches(1) millimeters Symbol Min Typ Max Min Typ Max E1 13.800 14.000 14.200 0.5433 0.5512 0.5591 E3 - 12.000 - - 0.4724 - e - 0.500 - - 0.0197 - L 0.450 0.600 0.750 0.0177 0.0236 0.0295 L1 - 1.000 - - 0.0394 - k 0.0° 3.5° 7.0° 0.0° 3.5° 7.0° ccc - - 0.080 - - 0.0031 1. Values in inches are converted from mm and rounded to 4 decimal digits. Figure 38.
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Package information STM32F071x8 STM32F071xB Device marking The following figure gives an example of topside marking orientation versus pin 1 identifier location. Other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below. Figure 39. LQFP100 package marking example KƉƚŝŽŶĂů ŐĂƚĞ ŵĂƌŬ WƌŽĚƵĐƚ ŝĚĞŶƚŝĨŝĐĂƚŝŽŶ ;ϭͿ 670 ) ZĞǀŝƐŝŽŶ ĐŽĚĞ 9%7 5 ĂƚĞ ĐŽĚĞ < :: WŝŶ ϭ ŝĚĞŶƚŝĨŝĞƌ D^ϯϵϬϭϭsϭ 1.
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STM32F071x8 STM32F071xB 7.3 Package information LQFP64 package information LQFP64 is a 64-pin, 10 x 10 mm low-profile quad flat package. Figure 40. LQFP64 package outline PP *$8*( 3/$1( F $ $ $ 6($7,1* 3/$1( & $ FFF & ' ' ' . / / ( ( ( E 3,1 ,'(17,),&$7,21 H :B0(B9 1. Drawing is not to scale. Table 73. LQFP64 package mechanical data inches(1) millimeters Symbol Min Typ Max Min Typ Max A - - 1.600 - - 0.0630 A1 0.050 - 0.
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Package information STM32F071x8 STM32F071xB Table 73. LQFP64 package mechanical data (continued) inches(1) millimeters Symbol Min Typ Max Min Typ Max E3 - 7.500 - - 0.2953 - e - 0.500 - - 0.0197 - K 0° 3.5° 7° 0° 3.5° 7° L 0.450 0.600 0.750 0.0177 0.0236 0.0295 L1 - 1.000 - - 0.0394 - ccc - - 0.080 - - 0.0031 1. Values in inches are converted from mm and rounded to 4 decimal digits. Figure 41.
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STM32F071x8 STM32F071xB Package information Device marking The following figure gives an example of topside marking orientation versus pin 1 identifier location. Other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below. Figure 42. LQFP64 package marking example ZĞǀŝƐŝŽŶ ĐŽĚĞ 5 WƌŽĚƵĐƚ ŝĚĞŶƚŝĨŝĐĂƚŝŽŶ ;ϭͿ 670 ) 5%7 < :: WŝŶ ϭ ŝĚĞŶƚŝĨŝĞƌ ĂƚĞ ĐŽĚĞ D^ϯϵϬϭϮsϭ 1.
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Package information 7.4 STM32F071x8 STM32F071xB WLCSP49 package information WLCSP49 is a 49-ball, 3.277 x 3.109 mm, 0.4 mm pitch wafer-level chip-scale package. Figure 43. WLCSP49 package outline H EEE = ) $ EDOO ORFDWLRQ $ * 'HWDLO $ H ( H * $ $ H %XPS VLGH 6LGH YLHZ $ )URQW YLHZ %XPS ' $ HHH = E 6HDWLQJ SODQH ( 'HWDLO $ URWDWHG $ RULHQWDWLRQ UHIHUHQFH DDD ; :DIHU EDFN VLGH 1. Drawing is not to scale. 106/122 Downloaded from Arrow.com.
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STM32F071x8 STM32F071xB Package information Table 74. WLCSP49 package mechanical data inches(1) millimeters Symbol Min Typ Max Min Typ Max A 0.525 0.555 0.585 0.0207 0.0219 0.0230 A1 - 0.175 - - 0.0069 - A2 - 0.380 - - 0.0150 - - 0.025 - - 0.0010 - b(3) 0.220 0.250 0.280 0.0087 0.0098 0.0110 D 3.242 3.277 3.312 0.1276 0.1290 0.1304 E 3.074 3.109 3.144 0.1210 0.1224 0.1238 e - 0.400 - - 0.0157 - e1 - 2.400 - - 0.0945 - e2 - 2.
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Package information STM32F071x8 STM32F071xB Device marking The following figure gives an example of topside marking orientation versus ball A1 identifier location. Other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below. Figure 44. WLCSP49 package marking example Žƚ ĞǀŝĐĞ ŝĚĞŶƚŝĨŝĐĂƚŝŽŶ ϭ ) &%< ĂƚĞ ĐŽĚĞ < :: 5 ZĞǀŝƐŝŽŶ ĐŽĚĞ D^ϯϵϬϭϯsϭ 1.
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STM32F071x8 STM32F071xB 7.5 Package information LQFP48 package information LQFP48 is a 48-pin, 7 x 7 mm low-profile quad flat package. Figure 45. LQFP48 package outline F $ $ $ 6($7,1* 3/$1( & PP *$8*( 3/$1( FFF & . $ ' ' / / ' 3,1 ,'(17,),&$7,21 ( ( ( E H %B0(B9 1. Drawing is not to scale. DocID025451 Rev 6 109/122 118 Downloaded from Arrow.com.
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Package information STM32F071x8 STM32F071xB Table 75. LQFP48 package mechanical data inches(1) millimeters Symbol Min Typ Max Min Typ Max A - - 1.600 - - 0.0630 A1 0.050 - 0.150 0.0020 - 0.0059 A2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.170 0.220 0.270 0.0067 0.0087 0.0106 c 0.090 - 0.200 0.0035 - 0.0079 D 8.800 9.000 9.200 0.3465 0.3543 0.3622 D1 6.800 7.000 7.200 0.2677 0.2756 0.2835 D3 - 5.500 - - 0.2165 - E 8.800 9.000 9.200 0.
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STM32F071x8 STM32F071xB Package information Device marking The following figure gives an example of topside marking orientation versus pin 1 identifier location. Other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below. Figure 47. LQFP48 package marking example WƌŽĚƵĐƚ ŝĚĞŶƚŝĨŝĐĂƚŝŽŶ ;ϭͿ 670 ) &%7 WŝŶ ϭ ŝĚĞŶƚŝĨŝĞƌ < ĂƚĞ ĐŽĚĞ :: 5 ZĞǀŝƐŝŽŶ ĐŽĚĞ D^ϯϵϬϭϱsϭ 1.
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Package information 7.6 STM32F071x8 STM32F071xB UFQFPN48 package information UFQFPN48 is a 48-lead, 7x7 mm, 0.5 mm pitch, ultra-thin fine-pitch quad flat package. Figure 48. UFQFPN48 package outline 3LQ LGHQWLILHU ODVHU PDUNLQJ DUHD ' $ ( ( 7 GGG $ 6HDWLQJ SODQH E H 'HWDLO < ' ([SRVHG SDG DUHD < ' / & [ SLQ FRUQHU ( 5 W\S 'HWDLO = = $ % B0(B9 1. Drawing is not to scale. 2.
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STM32F071x8 STM32F071xB Package information Table 76. UFQFPN48 package mechanical data inches(1) millimeters Symbol Min Typ Max Min Typ Max A 0.500 0.550 0.600 0.0197 0.0217 0.0236 A1 0.000 0.020 0.050 0.0000 0.0008 0.0020 D 6.900 7.000 7.100 0.2717 0.2756 0.2795 E 6.900 7.000 7.100 0.2717 0.2756 0.2795 D2 5.500 5.600 5.700 0.2165 0.2205 0.2244 E2 5.500 5.600 5.700 0.2165 0.2205 0.2244 L 0.300 0.400 0.500 0.0118 0.0157 0.0197 T - 0.152 - - 0.
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Package information STM32F071x8 STM32F071xB Device marking The following figure gives an example of topside marking orientation versus pin 1 identifier location. Other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below. Figure 50. UFQFPN48 package marking example WƌŽĚƵĐƚ ŝĚĞŶƚŝĨŝĐĂƚŝŽŶ ϭ 670 ) &%8 ĂƚĞ ĐŽĚĞ < :: WŝŶ ϭ ŝĚĞŶƚŝĨŝĐĂƚŝŽŶ ZĞǀŝƐŝŽŶ ĐŽĚĞ 5 D^ϯϵϬϭϰsϭ 1.
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STM32F071x8 STM32F071xB 7.7 Package information Thermal characteristics The maximum chip junction temperature (TJmax) must never exceed the values given in Table 24: General operating conditions.
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Package information STM32F071x8 STM32F071xB As applications do not commonly use the STM32F071x8/xB at maximum dissipation, it is useful to calculate the exact power consumption and junction temperature to determine which temperature range will be best suited to the application. The following examples show how to calculate the temperature range needed for a given application.
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STM32F071x8 STM32F071xB Package information This is above the range of the suffix 6 version parts (–40 < TJ < 105 °C). In this case, parts must be ordered at least with the temperature range suffix 7 (see Section 8: Ordering information) unless we reduce the power dissipation in order to be able to use suffix 6 parts. Refer to Figure 51 to select the required temperature range (suffix 6 or 7) according to your temperature or power requirements. Figure 51.
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Ordering information 8 STM32F071x8 STM32F071xB Ordering information For a list of available options (memory, package, and so on) or for further information on any aspect of this device, please contact your nearest ST sales office. Table 78.
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STM32F071x8 STM32F071xB 9 Revision history Revision history Table 79. Document revision history Date Revision 13-Jan-2014 1 Initial draft 2 Added part number STM32F071V8. Changed status of document from “Preliminary data” to “Production data”. Updated “Reset and power management” data in Features. Updated tS_vrefint in Table: Embedded internal reference voltage. Updated VHSEH and VHSEL in Table: High-speed external user clock characteristics.
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Revision history STM32F071x8 STM32F071xB Table 79. Document revision history (continued) Date 17-Dec-2015 14-Jun-2016 120/122 Downloaded from Arrow.com.
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STM32F071x8 STM32F071xB Revision history Table 79. Document revision history (continued) Date 15-Sep-2016 10-Jan-2017 Revision Changes 5 Section 6: Electrical characteristics: – Figure 29: SPI timing diagram - slave mode and CPHA = 0 and Figure 30: SPI timing diagram - slave mode and CPHA = 1 updated - modified NSS timing waveforms (among other changes) 6 Section 6: Electrical characteristics: – Table 40: LSE oscillator characteristics (fLSE = 32.
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STM32F071x8 STM32F071xB IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement.