Datasheet

Electrical characteristics STM32F070xB STM32F070x6
48/88 DocID027114 Rev 2
6.3.6 Wakeup time from low-power mode
The wakeup times given in Table 30 are the latency between the event and the execution of
the first user instruction. The device goes in low-power mode after the WFE (Wait For
Event) instruction, in the case of a WFI (Wait For Interruption) instruction, 16 CPU cycles
must be added to the following timings due to the interrupt latency in the Cortex M0
architecture.
The SYSCLK clock source setting is kept unchanged after wakeup from Sleep mode.
During wakeup from Stop or Standby mode, SYSCLK takes the default setting: HSI 8 MHz.
The wakeup source from Sleep and Stop mode is an EXTI line configured in event mode.
The wakeup source from Standby mode is the WKUP1 pin (PA0).
All timings are derived from tests performed under the ambient temperature and supply
voltage conditions summarized in Table 21: General operating conditions.
Table 30. Low-power mode wakeup timings
Symbol Parameter Conditions
Typ @VDD =
VDDA
Max Unit
= 3.3 V
t
WUSTOP
Wakeup from Stop mode Regulator in run mode 2.8 5
μs
t
WUSTANDBY
Wakeup from Standby mode - 51 -
t
WUSLEEP
Wakeup from Sleep mode -
4 SYSCLK
cycles
-
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