Datasheet

Functional overview STM32F070xB STM32F070x6
22/88 DocID027114 Rev 2
In addition, I2C1 provides hardware support for SMBUS 2.0 and PMBUS 1.1: ARP
capability, Host notify protocol, hardware CRC (PEC) generation/verification, timeouts
verifications and ALERT protocol management.
The I2C interfaces can be served by the DMA controller.
Refer to Table 7 for the differences between I2C1 and I2C2.
3.14 Universal synchronous/asynchronous receiver transmitters
(USART)
The device embeds up to four universal synchronous/asynchronous receiver transmitters
(USART1, USART2 and USART3, USART4 on STM32F070xB devices only), which
communicate at speeds of up to 6 Mbit/s.
They provide hardware management of the CTS and RTS signals, multiprocessor
communication mode, master synchronous communication and single-wire half-duplex
communication mode. USART1 supports also the auto baud rate feature.
The USART interfaces can be served by the DMA controller.
Table 7. STM32F070xB/6 I
2
C implementation
I2C features
(1)
1. X = supported.
I2C1 I2C2
(2)
2. Only available on STM32F070xB devices.
7-bit addressing mode X X
10-bit addressing mode X X
Standard mode (up to 100 kbit/s) X X
Fast mode (up to 400 kbit/s) X X
Fast Mode Plus (up to 1 Mbit/s) with 20mA
output drive I/Os X -
Independent clock X -
SMBus X -
Wakeup from STOP - -
Table 8. STM32F070xB/6 USART implementationF070
(1)
1. Where X means supported.
USART modes/features USART1 and USART2 USART3
(2)
and USART4
(2)
2. Not available on STM32F070x6 devices.
Hardware flow control for modem X X
Continuous communication using DMA X X
Multiprocessor communication X X
Synchronous mode X X
Single-wire half-duplex communication X X
Receiver timeout interrupt X -
Auto baud rate detection X -
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