Datasheet

DocID022265 Rev 6 89/121
STM32F051x4 STM32F051x6 STM32F051x8 Electrical characteristics
90
Figure 32. I
2
S slave timing diagram (Philips protocol)
1. Measurement points are done at CMOS levels: 0.3 × V
DDIOx
and 0.7 × V
DDIOx
.
2. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first
byte.
t
su(SD_MR)
Data input setup time
Master receiver 6 -
ns
t
su(SD_SR)
Slave receiver 2 -
t
h(SD_MR)
(2)
Data input hold time
Master receiver 4 -
t
h(SD_SR)
(2)
Slave receiver 0.5 -
t
v(SD_MT)
(2)
Data output valid time
Master transmitter - 4
t
v(SD_ST)
(2)
Slave transmitter - 20
t
h(SD_MT)
Data output hold time
Master transmitter 0 -
t
h(SD_ST)
Slave transmitter 13 -
1. Data based on design simulation and/or characterization results, not tested in production.
2. Depends on f
PCLK
. For example, if f
PCLK
= 8 MHz, then T
PCLK
= 1/f
PLCLK
= 125 ns.
Table 64. I
2
S characteristics
(1)
(continued)
Symbol Parameter Conditions Min Max Unit
06Y9
&.,QSXW
&32/ 
&32/ 
WF&.
:6LQSXW
6'WUDQVPLW
6'UHFHLYH
WZ&.+
WZ&./
WVX:6
WY6'B67 WK6'B67
WK:6
WVX6'B65 WK6'B65
06%UHFHLYH %LWQUHFHLYH /6%UHFHLYH
06%WUDQVPLW %LWQWUDQVPLW
/6%UHFHLYH
/6%WUDQVPLW
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