Datasheet

DocID025743 Rev 6 71/106
STM32F031x4 STM32F031x6 Electrical characteristics
80
Equation 1: R
AIN
max formula
The formula above (Equation 1) is used to determine the maximum external impedance
allowed for an error below 1/4 of LSB. Here N = 12 (from 12-bit resolution).
W
LATENCY
(2)(4)
ADC_DR register ready
latency
ADC clock = HSI14
1.5 ADC
cycles + 2
f
PCLK
cycles
-
1.5 ADC
cycles + 3
f
PCLK
cycles
-
ADC clock = PCLK/2 - 4.5 -
f
PCLK
cycle
ADC clock = PCLK/4 - 8.5 -
f
PCLK
cycle
t
latr
(2)
Trigger conversion latency
f
ADC
= f
PCLK
/2 = 14 MHz 0.196 µs
f
ADC
= f
PCLK
/2 5.5 1/f
PCLK
f
ADC
= f
PCLK
/4 = 12 MHz 0.219 µs
f
ADC
= f
PCLK
/4 10.5 1/f
PCLK
f
ADC
= f
HSI14
= 14 MHz 0.179 - 0.250 µs
Jitter
ADC
ADC jitter on trigger
conversion
f
ADC
= f
HSI14
-1-1/f
HSI14
t
S
(2)
Sampling time
f
ADC
= 14 MHz 0.107 - 17.1 µs
- 1.5 - 239.5 1/f
ADC
t
STAB
(2)
Stabilization time - 14 1/f
ADC
t
CONV
(2)
Total conversion time
(including sampling time)
f
ADC
= 14 MHz,
12-bit resolution
1-18µs
12-bit resolution
14 to 252 (t
S
for sampling +12.5 for
successive approximation)
1/f
ADC
1. During conversion of the sampled value (12.5 x ADC clock period), an additional consumption of 100 µA on I
DDA
and 60 µA
on I
DD
should be taken into account.
2. Guaranteed by design, not tested in production.
3. Specified value includes only ADC timing. It does not include the latency of the register access.
4. This parameter specify latency for transfer of the conversion result to the ADC_DR register. EOC flag is set at this time.
Table 50. ADC characteristics (continued)
Symbol Parameter Conditions Min Typ Max Unit
R
AIN
T
S
f
ADC
C
ADC
2
N2+
()ln××
--------------------------------------------------------------- - R
ADC
–<
Table 51. R
AIN
max for f
ADC
= 14 MHz
T
s
(cycles) t
S
(µs) R
AIN
max (kΩ)
(1)
1.5 0.11 0.4
7.5 0.54 5.9
13.5 0.96 11.4
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