Datasheet

Electrical characteristics STM32F030x4/x6/x8/xC
70/93 DS9773 Rev 4
Figure 23. ADC accuracy characteristics
Figure 24. Typical connection diagram using the ADC
1. Refer to Table 50: ADC characteristics for the values of R
AIN
, R
ADC
and C
ADC
.
2. C
parasitic
represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the
pad capacitance (roughly 7
pF). A high C
parasitic
value will downgrade conversion accuracy. To remedy
this, f
ADC
should be reduced.
General PCB design guidelines
Power supply decoupling should be performed as shown in Figure 13: Power supply
scheme. The 10 nF capacitor should be ceramic (good quality) and it should be placed as
close as possible to the chip.
E T = total unajusted error: maximum deviation
between the actual and ideal transfer curves.
E
O = offset error: maximum deviation
between the first actual transition and
the first ideal one.
E
G = gain error: deviation between the last
ideal transition and the last actual one.
E D = differential linearity error: maximum
deviation between actual steps and the ideal ones.
E
L = integral linearity error: maximum deviation
between any actual transition and the end point
correlation line.
(1) Example of an actual transfer curve
(2) The ideal transfer curve
(3) End point correlation line
4095
4094
4093
7
6
5
4
3
2
1
0
23456
1
7 4093
4094 4095
4096
V DDA
V SSA
EO
ET
EL
EG
ED
1 LSB IDEAL
(1)
(3)
(2)
MS19880V2
MS33900V1
V
DDA
AINx
I
L
±1 μA
V
T
R
AIN
(1)
C
parasitic
V
AIN
V
T
R
ADC
12-bit
con ver ter
C
ADC
Sample and hold ADC
con ver ter