Datasheet

Functional overview STM32F030x4/x6/x8/xC
22/93 DS9773 Rev 4
3.13 Inter-integrated circuit interfaces (I
2
C)
Up to two I2C interfaces (I2C1 and I2C2) can operate in multimaster or slave modes. Both
can support Standard mode (up to 100 kbit/s) or Fast mode (up to 400 kbit/s). I2C1 also
supports Fast Mode Plus (up to 1 Mbit/s), with 20 mA output drive.
Both support 7-bit and 10-bit addressing modes, multiple 7-bit slave addresses (two
addresses, one with configurable mask). They also include programmable analog and
digital noise filters.
In addition, I2C1 provides hardware support for SMBUS 2.0 and PMBUS 1.1: ARP
capability, Host notify protocol, hardware CRC (PEC) generation/verification, timeouts
verifications and ALERT protocol management
The I2C interfaces can be served by the DMA controller.
Refer to Table 7 for the differences between I2C1 and I2C2.
3.14 Universal synchronous/asynchronous receiver/transmitter
(USART)
The device embeds up to six universal synchronous/asynchronous receivers/transmitters
that communicate at speeds of up to 6
Mbit/s.
Table 6. Comparison of I2C analog and digital filters
- Analog filter Digital filter
Pulse width of
suppressed spikes
≥ 50 ns
Programmable length from 1 to 15
I2C peripheral clocks
Benefits Available in Stop mode
1. Extra filtering capability vs.
standard requirements.
2. Stable length
Drawbacks
Variations depending on
temperature, voltage, process
-
Table 7. STM32F030x4/x6/x8/xC I
2
C implementation
(1)
1. X = supported.
I2C features I2C1 I2C2
(2)
2. Only available on STM32F030x8/C devices.
7-bit addressing mode X X
10-bit addressing mode X X
Standard mode (up to 100 kbit/s) X X
Fast mode (up to 400 kbit/s) X X
Fast Mode Plus (up to 1 Mbit/s), with 20mA
output drive I/Os X -
Independent clock X -
SMBus X -
Wakeup from STOP - -