Datasheet

ST7LITE0xY0, ST7LITESxY0
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13.5 CLOCK AND TIMING CHARACTERISTICS
Subject to general operating conditions for V
DD
, f
OSC
, and T
A
.
13.5.1 General Timings
13.5.2 External Clock Source
Notes:
1. Guaranteed by Design. Not tested in production.
2. Data based on typical application software.
3. Time measured between interrupt event and interrupt vector fetch. ∆t
c(INST)
is the number of t
CPU
cycles needed to fin-
ish the current instruction execution.
4. Data based on design simulation and/or technology characteristics, not tested in production.
Figure 61. Typical Application with an External Clock Source
Symbol Parameter
1)
Conditions Min Typ
2)
Max Unit
t
c(INST)
Instruction cycle time f
CPU
=8MHz
2312t
CPU
250 375 1500 ns
t
v(IT)
Interrupt reaction time
3)
t
v(IT)
= ∆t
c(INST)
+ 10
f
CPU
=8MHz
10 22 t
CPU
1.25 2.75 µs
Symbol Parameter Conditions Min Typ Max Unit
V
CLKINH
CLKIN input pin high level voltage
see Figure 61
0.7xV
DD
V
DD
V
V
CLKINL
CLKIN input pin low level voltage V
SS
0.3xV
DD
t
w(CLKINH)
t
w(CLKINL)
CLKIN high or low time
4)
15
ns
t
r(CLKIN)
t
f(CLKIN)
CLKIN rise or fall time
4)
15
I
L
CLKIN Input leakage current V
SS
≤V
IN
≤V
DD
±1 µA
CLKIN
f
OSC
EXTERNAL
ST72XXX
CLOCK SOURCE
V
CLKINL
V
CLKINH
t
r(CLKIN)
t
fCLKIN)
t
w(CLKINH)
t
w(CLKINL)
I
L
90%
10%
1