Datasheet

ST7LITE0xY0, ST7LITESxY0
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12.2 INSTRUCTION GROUPS
The ST7 family devices use an Instruction Set
consisting of 63 instructions. The instructions may
be subdivided into 13 main groups as illustrated in
the following table:
Using a prebyte
The instructions are described with 1 to 4 bytes.
In order to extend the number of available op-
codes for an 8-bit CPU (256 opcodes), three differ-
ent prebyte opcodes are defined. These prebytes
modify the meaning of the instruction they pre-
cede.
The whole instruction becomes:
PC-2 End of previous instruction
PC-1 Prebyte
PC Opcode
PC+1 Additional word (0 to 2) according to the
number of bytes required to compute the
effective address
These prebytes enable instruction in Y as well as
indirect addressing modes to be implemented.
They precede the opcode of the instruction in X or
the instruction using direct addressing mode. The
prebytes are:
PDY 90 Replace an X based instruction using
immediate, direct, indexed, or inherent
addressing mode by a Y one.
PIX 92 Replace an instruction using direct, di-
rect bit or direct relative addressing
mode to an instruction using the corre-
sponding indirect addressing mode.
It also changes an instruction using X
indexed addressing mode to an instruc-
tion using indirect X indexed addressing
mode.
PIY 91 Replace an instruction using X indirect
indexed addressing mode by a Y one.
12.2.1 Illegal Opcode Reset
In order to provide enhanced robustness to the de-
vice against unexpected behavior, a system of ille-
gal opcode detection is implemented. If a code to
be executed does not correspond to any opcode
or prebyte value, a reset is generated. This, com-
bined with the Watchdog, allows the detection and
recovery from an unexpected fault or interference.
Note: A valid prebyte associated with a valid op-
code forming an unauthorized combination does
not generate a reset.
Load and Transfer LD CLR
Stack operation PUSH POP RSP
Increment/Decrement INC DEC
Compare and Tests CP TNZ BCP
Logical operations AND OR XOR CPL NEG
Bit Operation BSET BRES
Conditional Bit Test and Branch BTJT BTJF
Arithmetic operations ADC ADD SUB SBC MUL
Shift and Rotates SLL SRL SRA RLC RRC SWAP SLA
Unconditional Jump or Call JRA JRT JRF JP CALL CALLR NOP RET
Conditional Branch JRxx
Interruption management TRAP WFI HALT IRET
Condition Code Flag modification SIM RIM SCF RCF
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