ST7LITE0xY0, ST7LITESxY0
71/124
Figure 44. ADC Block Diagram
CH2 CH10EOC SPEED ADON 0 CH0
ADCCSR
AIN0
AIN1
ANALOG TO DIGITAL
CONVERTER
AINx
ANALOG
MUX
R
ADC
C
ADC
D2 D1D3D7 D6 D5 D4 D0
ADCDR
3
f
ADC
HOLD CONTROL
x 1 or
x 8
AMPSEL bit
(ADCAMP Register)
f
CPU
0
1
1
0
DIV 2
DIV 4
SLOW
bit
(ADCAMP Register)
7
0
1
