Datasheet

ST7LITE0xY0, ST7LITESxY0
28/124
RESET SEQUENCE MANAGER (Cont’d)
7.4.2 Asynchronous External RESET
pin
The RESET
pin is both an input and an open-drain
output with integrated R
ON
weak pull-up resistor.
This pull-up has no fixed value but varies in ac-
cordance with the input voltage. It
can be pulled
low by external circuitry to reset the device. See
Electrical Characteristic section for more details.
A RESET signal originating from an external
source must have a duration of at least t
h(RSTL)in
in
order to be recognized (see Figure 17). This de-
tection is asynchronous and therefore the MCU
can enter reset state even in HALT mode.
The RESET
pin is an asynchronous signal which
plays a major role in EMS performance. In a noisy
environment, it is recommended to follow the
guidelines mentioned in the electrical characteris-
tics section.
7.4.3 External Power-On RESET
If the LVD is disabled by option byte, to start up the
microcontroller correctly, the user must ensure by
means of an external reset circuit that the reset
signal is held low until V
DD
is over the minimum
level specified for the selected f
OSC
frequency.
A proper reset signal for a slow rising V
DD
supply
can generally be provided by an external RC net-
work connected to the RESET
pin.
7.4.4 Internal Low Voltage Detector (LVD)
RESET
Two different RESET sequences caused by the in-
ternal LVD circuitry can be distinguished:
■ Power-On RESET
■ Voltage Drop RESET
The device RESET
pin acts as an output that is
pulled low when V
DD
<V
IT+
(rising edge) or
V
DD
<V
IT-
(falling edge) as shown in Figure 17.
The LVD filters spikes on V
DD
larger than t
g(VDD)
to
avoid parasitic resets.
7.4.5 Internal Watchdog RESET
The RESET sequence generated by a internal
Watchdog counter overflow is shown in Figure 17.
Starting from the Watchdog counter underflow, the
device RESET
pin acts as an output that is pulled
low during at least t
w(RSTL)out
.
Figure 17. RESET Sequences
V
DD
RUN
RESET PIN
EXTERNAL
WATCHDOG
ACTIVE PHASE
V
IT+(LVD)
V
IT-(LVD)
t
h(RSTL)in
RUN
WATCHDOG UNDERFLOW
t
w(RSTL)out
RUN RUN
RESET
RESET
SOURCE
EXTERNAL
RESET
LVD
RESET
WATCHDOG
RESET
INTERNAL RESET (256 T
CPU
)
VECTOR FETCH
ACTIVE
PHASE
ACTIVE
PHASE
1