Datasheet

ST7LITE0xY0, ST7LITESxY0

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DATA EEPROM (Cont’d)

5.7 REGISTER DESCRIPTION

EEPROM CONTROL/STATUS REGISTER (EEC-

SR)

Read/Write

Reset Value: 0000 0000 (00h)

Bits 7:2 = Reserved, forced by hardware to 0.

Bit 1 = E2LAT Latch Access Transfer

This bit is set by software. It is cleared by hard-

ware at the end of the programming cycle. It can

only be cleared by software if the E2PGM bit is

cleared.

0: Read mode

1: Write mode

Bit 0 = E2PGM Programming control and status

This bit is set by software to begin the programming

cycle. At the end of the programming cycle, this bit

is cleared by hardware.

0: Programming finished or not yet started

1: Programming cycle is in progress

Note: If the E2PGM bit is cleared during the pro-

gramming cycle, the memory data is not guaran-

teed.

Table 4. DATA EEPROM Register Map and Reset Values

000000E2LATE2PGM

Address

(Hex.)

Label

76543210

0030h

EECSR

Reset Value

000000

E2LAT

E2PGM