Datasheet

ST7LITE0xY0, ST7LITESxY0
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DATA EEPROM (Cont’d)
Figure 9. Data E
2
PROM Write Operation
Note: If a programming cycle is interrupted (by RESET action), the integrity of the data in memory will not
be guaranteed.
Byte 1 Byte 2 Byte 32
PHASE 1
Programming cycle
Read operation impossible
PHASE 2
Read operation possible
E2LAT bit
E2PGM bit
Writing data latches Waiting E2PGM and E2LAT to fall
Set by USER application
Cleared by hardware
⇓ Row / Byte ⇒ 0 1 2 3 ... 30 31 Physical Address
0
00h...1Fh
1
20h...3Fh
...
N
Nx20h...Nx20h+1Fh
ROW
DEFINITION
1