Datasheet

ST6200C/ST6201C/ST6203C
68/100
10.5 CLOCK AND TIMING CHARACTERISTICS
Subject to general operating conditions for V
DD
, f
OSC
, and T
A
.
10.5.1 General Timings
10.5.2 External Clock Source
Notes:
1. Data based on typical application software.
2. Time measured between interrupt event and interrupt vector fetch.
∆
t
c(INST)
is the number of t
CPU
cycles needed to finish
the current instruction execution.
Figure 43. Typical Application with an External Clock Source
Symbol Parameter Conditions Min Typ
1)
Max Unit
t
c(INST)
Instruction cycle time
245t
CPU
f
CPU
=8 MHz 3.25 6.5 8.125
µ
s
t
v(IT)
Interrupt reaction time
2)
t
v(IT)
=
∆
t
c(INST)
+ 6
611t
CPU
f
CPU
=8 MHz 9.75 17.875
µ
s
Symbol Parameter Conditions Min Typ Max Unit
V
OSCINH
OSC
IN
input pin high level voltage
See Figure 43
0.7xV
DD
V
DD
V
V
OSCINL
OSC
IN
input pin low level voltage V
SS
0.3xV
DD
I
L
OSCx Input leakage current V
SS
≤
V
IN
≤
V
DD
± 2
µ
A
OSC
IN
OSC
OUT
f
OSC
EXTERNAL
ST62XX
CLOCK SOURCE
V
OSCINL
V
OSCINH
I
L
90%
10%
Not connected
1