Datasheet
ST6200C/ST6201C/ST6203C
47/100
8-BIT TIMER (Cont’d)
8.2.6 Register Description
PRESCALER COUNTER REGISTER (PSCR)
Address: 0D2h - Read/Write
Reset Value: 0111 1111 (7Fh)
Bit 7 = PSCR7: Not used, always read as “0”.
Bits 6:0 = PSCR[6:0]
Prescaler LSB.
TIMER COUNTER REGISTER (TCR)
Address: 0D3h - Read / Write
Reset Value: 1111 1111 (FFh)
Bits 7:0 = TCR[7:0]
Timer counter bits.
TIMER STATUS CONTROL REGISTER (TSCR)
Address: 0D4h - Read/Write
Reset Value: 0000 0000 (00h)
Bit 7 = TMZ
Timer Zero bit.
A low-to-high transition indicates that the timer
count register has underflowed. It means that the
TCR value has changed from 00h to FFh.
This bit must be cleared by user software.
0: Counter has not underflowed
1: Counter underflow occurred
Bit 6 = ETI
Enable Timer Interrupt.
When set, enables the timer interrupt request. If
ETI=0 the timer interrupt is disabled. If ETI=1 and
TMZ=1 an interrupt request is generated.
0: Interrupt disabled (reset state)
1: Interrupt enabled
Bit 5 = TSCR5 Reserved, must be set.
Bit 4 = TSCR4 Reserved, must be cleared.
Bit 3 = PSI:
Prescaler Initialize bit.
Used to initialize the prescaler and inhibit its count-
ing. When PSI=“0” the prescaler is set to 7Fh and
the counter is inhibited. When PSI=“1” the prescal-
er is enabled to count downwards. As long as
PSE=“1” both counter and prescaler are not run-
ning
0: Counting disabled
1: Counting enabled
Bits 1:0 = PS[2:0]
Prescaler Mux. Select.
These bits select the division ratio of the prescaler
register.
Table 12. Prescaler Division Factors
Table 13. 8-Bit Timer Register Map and Reset Values
70
PSCR
7
PSCR
6
PSCR
5
PSCR
4
PSCR
3
PSCR
2
PSCR
1
PSCR
0
70
TCR7 TCR6 TCR5 TCR4 TCR3 TCR2 TCR1 TCR0
70
TMZ ETI TSCR5 TSCR4 PSI PS2 PS1 PS0
PS2 PS1 PS0 Divided by
0 0 0 1
0 0 1 2
0 1 0 4
0118
10016
10132
11064
111128
Address
(Hex.)
Register Label 7 6 5 43210
0D2h
PSCR
Reset Value
PSCR7
0
PSCR6
1
PSCR5
1
PSCR4
1
PSCR3
1
PSCR2
1
PSCR1
1
PSCR0
1
0D3h
TCR
Reset Value
TCR7
1
TCR6
1
TCR5
1
TCR4
1
TCR3
1
TCR2
1
TCR1
1
TCR0
1
0D4h
TSCR
Reset Value
TMZ
0
ETI
0
TSCR5
0
TSCR4
0
PSI
0
PS2
0
PS1
0
PS0
0
1