Datasheet

ST6200C/ST6201C/ST6203C
41/100
8 ON-CHIP PERIPHERALS
8.1 WATCHDOG TIMER (WDG)
8.1.1 Introduction
The Watchdog timer is used to detect the occur-
rence of a software fault, usually generated by ex-
ternal interference or by unforeseen logical condi-
tions, which causes the application program to
abandon its normal sequence. The Watchdog cir-
cuit generates an MCU reset on expiry of a pro-
grammed time period, unless the program refresh-
es the counter’s contents before the SR bit be-
comes cleared.
8.1.2 Main Features
■ Programmable timer (64 steps of 3072 clock
cycles)
■ Software reset
■ Reset (if watchdog activated) when the SR bit
reaches zero
■ Hardware or software watchdog activation
selectable by option bit (Refer to the option
bytes section)
Figure 25. Watchdog Block Diagram
RESET
C
7-BIT DOWNCOUNTER
f
int /12
SR
T0
CLOCK DIVIDER
WATCHDOG REGISTER (WDGR)
÷
256
T1
T2
T3
T4
T5
bit 0
bit 7
1