Datasheet

ST6200C/ST6201C/ST6203C
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5.3 RESET
5.3.1 Introduction
The MCU can be reset in three ways:
■ A low pulse input on the RESET pin
■ Internal Watchdog reset
■ Internal Low Voltage Detector (LVD) reset
5.3.2 RESET Sequence
The basic RESET sequence consists of 3 main
phases:
■ Internal (watchdog or LVD) or external Reset
event
■ A delay of 2048 or 32768 clock (f
INT
) cycles
(selected through the option bytes)
■ RESET vector fetch
The reset delay allows the oscillator to stabilise
and ensures that recovery has taken place from
the Reset state.
The RESET vector fetch phase duration is 2 clock
cycles.
When a reset occurs:
– The stack is cleared
– The PC is loaded with the address of the Reset
vector. It is located in program ROM starting at
address 0FFEh.
A jump to the beginning of the user program must
be coded at this address.
– The interrupt flag is automatically set, so that the
CPU is in Non Maskable Interrupt mode. This
prevents the initialization routine from being in-
terrupted. The initialization routine should there-
fore be terminated by a RETI instruction, in order
to go back to normal mode.
Figure 13. RESET Sequence
V
DD
RESET PIN
WATCHDOG
V
IT+
V
IT-
WATCHDOG UNDERFLOW
RESET
2048 CLOCK CYCLE (f
INT
) DELAY
LVD
RESET
INTERNAL
RUN
RESET
RUN RUN RUN
RESET RESET
RESET
1