Datasheet

Test circuits and typical characteristics
ST3485EB, ST3485EC, ST3485EI, ST3485EIY
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DocID9102 Rev 11
Figure 12: Drive enable and disable times waveforms (pull-up configuration)
1. t
PZL
is valid if the driver is initially disabled ( RE is high), t
PSL
is valid if the driver is
initially in shutdown mode (RE is low).
Figure 13: Receiver propagation delay time test circuit
1. The input pulse is supplied by a generator with the following characteristics: PRR =
250 kHz, 50 % duty cycle, tr ≤ 6.0 ns.
2. C
L
includes probe and stray capacitance
IN
OUT
t
PZL
or t
PSL
(1)
V
OM
1.5 V 1.5 V
t
PLZ
0.25 V
3 V
0 V
V
CC
V
OL
IN
(1)
V
ID
R
OUT
C
L
= 1.5 pF
(2)
1.5 V
0 V