Datasheet

ST3485EB, ST3485EC, ST3485EI, ST3485EIY
Test circuits and typical characteristics
DocID9102 Rev 11
11/24
Figure 5: Drive differential output delay transition time test circuit
1. The input pulse is supplied by a generator with the following characteristics: PRR =
250 kHz, 50 % duty cycle, tr ≤ 6.0 ns, Z
O
= 50 Ω.
2. C
L
includes probe and stray capacitance
Figure 6: Drive differential output delay transition time waveform
Figure 7: Drive enable and disable times test circuit (pull-down configuration)
1. The input pulse is supplied by a generator with the following characteristics: PRR =
250 kHz, 50 % duty cycle, tr ≤ 6.0 ns.
2. C
L
includes probe and stray capacitance
IN
(1)
D
V
CC
C
L
R
L
= 60 Ω
C
L
= 15 pF
(2)
OUT
IN
OUT
1.5 V
t
DO
t
DD
3 V
0 V
2 V
-2 V
50 %
10 %
90 %
t
TD
1.5 V
t
TD
50 %
10 %
90 %
0 V or 3 V
IN
(1)
D
S1
C
L
= 50 pF
(2)
R
L
= 110 Ω
OUT