Datasheet

Instructions M95M01-DF M95M01-R
24/45 Doc ID 13264 Rev 11
The instruction is not accepted, and is not executed, under the following conditions:
● if the Write Enable Latch (WEL) bit has not been set to 1 (by executing a Write Enable
instruction just before),
● if a Write cycle is already in progress,
● if the device has not been deselected, by driving high Chip Select (S), at a byte
boundary (after the eighth bit, b0, of the last data byte that has been latched in),
● if the addressed page is in the region protected by the Block Protect (BP1 and BP0)
bits.
Note: The self-timed write cycle t
W
is internally executed as a sequence of two consecutive
events: [Erase addressed byte(s)], followed by [Program addressed byte(s)]. An erased bit is
read as “0” and a programmed bit is read as “1”.
Figure 14. Page Write (WRITE) sequence
MS30906V1
C
D
S
C
D
S
23
21 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35
22 21
3210
36 37 38
Instruction 24-bit address
0
765432 0
1
Data byte 1
39
765432 0
1
Data byte 2
765432 0
1
Data byte 3
65432 0
1
Data byte N