Datasheet

M93C46, M93C56, M93C66, M93C76, M93C86 DC and AC parameters
Doc ID 4997 Rev 12 25/34
Figure 9. Synchronous timing (start and op-code input)
Table 23. AC characteristics (M93Cx6-R)
Test conditions specified in Table 13 and Table 11
Symbol Alt. Parameter Min.
(1)
1. This product is under development. For more information, please contact your nearest ST sales office.
Max.
(1)
Unit
f
C
f
SK
Clock frequency D.C. 1 MHz
t
SLCH
Chip Select low to Clock high 250 ns
t
SHCH
t
CSS
Chip Select setup time 50 ns
t
SLSH
(2)
2. Chip Select Input (S) must be brought low for a minimum of t
SLSH
between consecutive instruction cycles.
t
CS
Chip Select low to Chip Select high 250 ns
t
CHCL
(3)
3. t
CHCL
+ t
CLCH
≥ 1 / f
C
.
t
SKH
Clock high time 250 ns
t
CLCH
(3)
t
SKL
Clock low time 250 ns
t
DVCH
t
DIS
Data in setup time 100 ns
t
CHDX
t
DIH
Data in hold time 100 ns
t
CLSH
t
SKS
Clock setup time (relative to S) 100 ns
t
CLSL
t
CSH
Chip Select hold time 0 ns
t
SHQV
t
SV
Chip Select to READY/BUSY status 400 ns
t
SLQZ
t
DF
Chip Select low to output Hi-Z 200 ns
t
CHQL
t
PD0
Delay to output low 400 ns
t
CHQV
t
PD1
Delay to output valid 400 ns
t
W
t
WP
Erase or Write cycle time 10 ms
AI01428
C
OP CODE OP CODE
START
S
D
OP CODE INPUTSTART
tDVCH
tSHCH
tCLSH tCHCL
tCLCH
tCHDX