Datasheet

M93C46, M93C56, M93C66, M93C76, M93C86 DC and AC parameters
Doc ID 4997 Rev 12 23/34
Table 20. AC characteristics (M93Cx6, device grade 6 or 3)
Test conditions specified in Table 12 and Table 9
Symbol Alt. Parameter Min. Max. Unit
f
C
f
SK
Clock frequency D.C. 2 MHz
t
SLCH
Chip Select low to Clock high 50 ns
t
SHCH
t
CSS
Chip Select setup time
M93C46, M93C56, M93C66
50 ns
Chip Select setup time
M93C76, M93C86
50 ns
t
SLSH
(1)
1. Chip Select Input (S) must be brought low for a minimum of t
SLSH
between consecutive instruction cycles.
t
CS
Chip Select low to Chip Select high 200 ns
t
CHCL
(2)
2. t
CHCL
+ t
CLCH
≥ 1 / f
C
.
t
SKH
Clock high time 200 ns
t
CLCH
(2)
t
SKL
Clock low time 200 ns
t
DVCH
t
DIS
Data in setup time 50 ns
t
CHDX
t
DIH
Data in hold time 50 ns
t
CLSH
t
SKS
Clock setup time (relative to S) 50 ns
t
CLSL
t
CSH
Chip Select hold time 0 ns
t
SHQV
t
SV
Chip Select to READY/BUSY status 200 ns
t
SLQZ
t
DF
Chip Select low to output Hi-Z 100 ns
t
CHQL
t
PD0
Delay to output low 200 ns
t
CHQV
t
PD1
Delay to output valid 200 ns
t
W
t
WP
Erase or Write cycle time 5 ms
Table 21. AC characteristics (M93Cx6-W, device grade 6)
Test conditions specified in Table 13 and Table 10
Symbol Alt. Parameter Min. Max. Unit
f
C
f
SK
Clock frequency D.C. 2 MHz
t
SLCH
Chip Select low to Clock high 50 ns
t
SHCH
t
CSS
Chip Select setup time 50 ns
t
SLSH
(1)
t
CS
Chip Select low to Chip Select high 200 ns
t
CHCL
(2)
t
SKH
Clock high time 200 ns
t
CLCH
(2)
t
SKL
Clock low time 200 ns
t
DVCH
t
DIS
Data in setup time 50 ns
t
CHDX
t
DIH
Data in hold time 50 ns
t
CLSH
t
SKS
Clock setup time (relative to S) 50 ns
t
CLSL
t
CSH
Chip Select hold time 0 ns
t
SHQV
t
SV
Chip Select to READY/BUSY status 200 ns