M48T58 M48T58Y 5.0V, 64 Kbit (8 Kb x 8) TIMEKEEPER® SRAM Features ■ Integrated, ultra low power SRAM, real time clock, power-fail control circuit and battery ■ BYTEWIDE™ RAM-like clock access ■ BCD coded year, month, day, date, hours, minutes, and seconds ■ Frequency test output for real time clock ■ Automatic power-fail chip deselect and write protection ■ Write protect voltages 28 1 PCDIP28 (PC) Battery/Crystal CAPHAT (VPFD = power-fail deselect voltage): – M48T58: VCC = 4.75 to 5.5V 4.
Contents M48T58, M48T58Y Contents 1 Summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 Operation modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3 Read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4 Write mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 5 Data retention mode . . . . .
M48T58, M48T58Y List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
List of figures M48T58, M48T58Y List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. 4/31 Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 DIP connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 SOIC connections .
M48T58, M48T58Y 1 Summary description Summary description The M48T58/Y TIMEKEEPER® RAM is a 8Kb x 8 non-volatile static RAM and real time clock. The monolithic chip is available in two special packages to provide a highly integrated battery backed-up memory and real time clock solution. The M48T58/Y is a non-volatile pin and function equivalent to any JEDEC standard 8Kb x 8 SRAM.
Summary description Table 1. M48T58, M48T58Y Signal names A0-A12 DQ0-DQ7 Figure 2. Address Inputs Data Inputs / Outputs FT Frequency Test Output (Open Drain) E1 Chip Enable 1 E2 Chip Enable 2 G Output Enable W WRITE Enable VCC Supply Voltage VSS Ground DIP connections FT A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS 1 28 2 27 3 26 4 25 5 24 6 23 7 M48T58 22 8 M48T58Y 21 9 20 10 19 11 18 12 17 13 16 14 15 VCC W E2 A8 A9 A11 G A10 E1 DQ7 DQ6 DQ5 DQ4 DQ3 AI01375B Figure 3.
M48T58, M48T58Y Figure 4.
Operation modes 2 M48T58, M48T58Y Operation modes As Figure 4 on page 7 shows, the static memory array and the quartz controlled clock oscillator of the M48T58/Y are integrated on one silicon chip. The two circuits are interconnected at the upper eight memory locations to provide user accessible BYTEWIDE™ clock information in the bytes with addresses 1FF8h-1FFFh. The clock locations contain the century, year, month, date, day, hour, minute, and second in 24 hour BCD format (except for the century).
M48T58, M48T58Y 3 Read mode Read mode The M48T58/Y is in the READ Mode whenever W (WRITE Enable) is high, E1 (Chip Enable 1) is low, and E2 (Chip Enable 2) is high. The unique address specified by the 13 Address Inputs defines which one of the 8,192 bytes of data is to be accessed. Valid data will be available at the Data I/O pins within Address Access time (tAVQV) after the last address input signal is stable, providing that the E1, E2, and G access times are also satisfied.
Read mode M48T58, M48T58Y Table 3.
M48T58, M48T58Y 4 Write mode Write mode The M48T58/Y is in the WRITE Mode whenever W and E1 are low and E2 is high. The start of a WRITE is referenced from the latter occurring falling edge of W or E1, or the rising edge of E2. A WRITE is terminated by the earlier rising edge of W or E1, or the falling edge of E2. The addresses must be held valid throughout the cycle.
Write mode Figure 7.
M48T58, M48T58Y Table 4.
Data retention mode 5 M48T58, M48T58Y Data retention mode With valid VCC applied, the M48T58/Y operates as a conventional BYTEWIDE™ static RAM. Should the supply voltage decay, the RAM will automatically power-fail deselect, write protecting itself when VCC falls within the VPFD (max), VPFD (min) window. All outputs become high impedance, and all inputs are treated as “don't care.
M48T58, M48T58Y 6 Clock operations 6.1 Reading the clock Clock operations Updates to the TIMEKEEPER® registers (see Table 5) should be halted before clock data is read to prevent reading data in transition. The BiPORT™ TIMEKEEPER cells in the RAM array are only data registers and not the actual clock counters, so updating the registers can be halted without disturbing the clock itself. Updating is halted when a '1' is written to the READ Bit, D6 in the Control Register 1FF8h.
Clock operations Table 5.
M48T58, M48T58Y Clock operations D5 is the Sign Bit; '1' indicates positive calibration, '0' indicates negative calibration. Calibration occurs within a 64 minute cycle. The first 62 minutes in the cycle may, once per minute, have one second either shortened by 128 or lengthened by 256 oscillator cycles. If a binary '1' is loaded into the register, only the first 2 minutes in the 64 minute cycle will be modified; if a binary 6 is loaded, the first 12 will be affected, and so on.
Clock operations Figure 8. M48T58, M48T58Y Crystal accuracy across temperature ppm 20 0 -20 -40 ΔF = -0.038 ppm (T - T )2 ± 10% 0 F C2 -60 T0 = 25 °C -80 -100 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 °C AI02124 Figure 9. Clock calibration NORMAL POSITIVE CALIBRATION NEGATIVE CALIBRATION AI00594B 6.5 Battery low flag The M48T58/Y automatically performs periodic battery voltage monitoring upon power-up.
M48T58, M48T58Y Clock operations Note: This will cause the clock to lose time during the interval the SNAPHAT battery/crystal top is disconnected. Note: Battery monitoring is a useful technique only when performed periodically. The M48T58/Y only monitors the battery when a nominal VCC is applied to the device. Thus applications which require extensive durations in the battery back-up mode should be powered-up periodically (at least once every few months) in order for this technique to be beneficial.
Maximum rating 7 M48T58, M48T58Y Maximum rating Stressing the device above the rating listed in the “Absolute Maximum Ratings” table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability.
M48T58, M48T58Y 8 DC and AC parameters DC and AC parameters This section summarizes the operating and measurement conditions, as well as the DC and AC characteristics of the device. The parameters in the following DC and AC Characteristic tables are derived from tests performed under the Measurement Conditions listed in Table 7. Designers should check that the operating conditions in their projects match the measurement conditions when using the quoted parameters. Table 7.
DC and AC parameters Table 9. M48T58, M48T58Y DC characteristics Symbol M48T58 Test condition(1) Parameter Unit Min ILI ILO(2) Input Leakage Current Output Leakage Current M48T58Y Max Min Max 0V ≤ VIN ≤ VCC ±1 ±1 µA 0V ≤ VOUT ≤ VCC ±1 ±1 µA Outputs open 50 50 mA ICC Supply Current ICC1 Supply Current (Standby) TTL E1 = VIH E2 = VIO 3 3 mA ICC2 Supply Current (Standby) CMOS E1 = VCC – 0.2V E2 = VSS + 0.2V 3 3 mA VIL Input Low Voltage –0.3 0.8 –0.3 0.
M48T58, M48T58Y Table 10. DC and AC parameters Power down/up AC characteristics Parameter(1) Symbol Min tPD E1 or W at VIH or E2 at VIL before Power Down tF(2) VPFD (max) to VPFD (min) VCC Fall Time tFB(3) VPFD (min) to VSS VCC Fall Time Max Unit 0 µs 300 µs M48T58 10 µs M48T58Y 10 µs tR VPFD (min) to VPFD (max) VCC Rise Time 10 µs tRB VSS to VPFD (min) VCC Rise Time 1 µs trec VPFD (max) to Inputs Recognized 40 200 ms 1.
Package mechanical data 9 M48T58, M48T58Y Package mechanical data In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a Lead-free second level interconnect. The category of second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark.
M48T58, M48T58Y Package mechanical data Figure 14. SOH28 – 28-lead plastic small outline, 4-socket battery SNAPHAT, package outline A2 A C B eB e CP D N E H A1 α L 1 SOH-A Note: Drawing is not to scale. Table 13. SOH28 – 28-lead plastic small outline, 4-socket battery SNAPHAT, package mech. data mm inches Symb Typ Min A Max Typ Min 3.05 Max 0.120 A1 0.05 0.36 0.002 0.014 A2 2.34 2.69 0.092 0.106 B 0.36 0.51 0.014 0.020 C 0.15 0.32 0.006 0.012 D 17.71 18.
Package mechanical data M48T58, M48T58Y Figure 15. SH – 4-pin SNAPHAT housing for 48mAh battery & crystal, package outline A1 A2 A3 A eA B L eB D E SHTK-A Note: Drawing is not to scale. Table 14. SH – 4-pin SNAPHAT housing for 48mAh battery & crystal, package mech. data mm inches Symb Typ Min A Typ Min 9.78 Max 0.385 A1 6.73 7.24 0.265 0.285 A2 6.48 6.99 0.255 0.275 A3 26/31 Max 0.38 0.015 B 0.46 0.56 0.018 0.022 D 21.21 21.84 0.835 0.860 E 14.22 14.99 0.
M48T58, M48T58Y Package mechanical data Figure 16. SH – 4-pin SNAPHAT housing for 120mAh battery & crystal, package outline A1 A2 A3 A eA B L eB D E SHTK-A Note: Drawing is not to scale. Table 15. SH – 4-pin SNAPHAT housing for 120mAh battery & crystal, package mech. data mm inches Symb Typ Min A Max Typ Min 10.54 Max 0.415 A1 8.00 8.51 0.315 0.335 A2 7.24 8.00 0.285 0.315 A3 0.38 0.015 B 0.46 0.56 0.018 0.022 D 21.21 21.84 0.835 0.860 E 17.27 18.03 0.
Part numbering 10 M48T58, M48T58Y Part numbering Table 16. Ordering information scheme Example: M48T 58 –70 MH 1 E Device type M48T Supply voltage and write protect voltage 58(1) = VCC = 4.75 to 5.5V; VPFD = 4.5 to 4.75V 58Y = VCC = 4.5 to 5.5V; VPFD = 4.2 to 4.
M48T58, M48T58Y Table 17.
Revision history 11 M48T58, M48T58Y Revision history Table 18. 30/31 Document revision history Date Revision Changes Jul-1999 1.0 First Issue 27-Jul-2000 1.1 Century Bit and Battery Low Flag Paragraphs added; Power Down/Up AC Characteristics Table and Waveforms changed (Table 10, Figure 12) 04-Jun-2001 2.0 Reformatted; temperature information added (Table 9, 3, 4, 10, 11) 31-Jul-2001 2.1 Formatting changes from recent document review findings 20-May-2002 2.
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