Datasheet

Operation M41T00S
10/28 Doc ID 10772 Rev 5
Figure 7. READ mode sequence
Figure 8. Alternative READ mode sequence
2.3 WRITE mode
In this mode the master transmitter transmits to the M41T00S slave receiver. Bus protocol is
shown in Figure 9. Following the START condition and slave address, a logic '0' (R/W
=0) is
placed on the bus and indicates to the addressed device that word address “An” will follow
and is to be written to the on-chip address pointer. The data word to be written to the
memory is strobed in next and the internal address pointer is incremented to the next
address location on the reception of an acknowledge clock. The M41T00S slave receiver
will send an acknowledge clock to the master transmitter after it has received the slave
address see Figure 6 on page 9 and again after it has received the word address and each
data byte.
AI00899
BUS ACTIVITY:
ACK
S
ACK ACK ACK
NO ACK
STOP
START
P
SDA LINE
BUS ACTIVITY:
MASTER
R/W
DATA n DATA n+1
DATA n+X
WORD
ADDRESS (An)
SLAVE
ADDRESS
S
START R/W
SLAVE
ADDRESS
ACK
AI00895
BUS ACTIVITY:
ACK
S
ACK ACK ACK
NO ACK
STOP START
PSDA LINE
BUS ACTIVITY:
MASTER
R/W
DATA n DATA n+1 DATA n+X
SLAVE
ADDRESS