Datasheet

Description M24C64-DF, M24C64-W, M24C64-R, M24C64-F
6/43 Doc ID 16891 Rev 21
1 Description
M24C64-x and M24C64-DF devices are I2C-compatible electrically erasable programmable
memories (EEPROM). They are organized as 8192 × 8 bits.
The M24C64-D also offers an additional page, named the Identification Page (32 bytes)
which can be written and (later) permanently locked in Read-only mode. This Identification
Page offers flexibility in the application board production line, as it can be used to store
unique identification parameters and/or parameters specific to the production line.
Figure 1. Logic diagram
I
2
C uses a two-wire serial interface, comprising a bidirectional data line and a clock line. The
devices carry a built-in 4-bit device type identifier code (1010) in accordance with the I
2
C
bus definition.
The device behaves as a slave in the I
2
C protocol, with all memory operations synchronized
by the serial clock. Read and Write operations are initiated by a Start condition, generated
by the bus master. The Start condition is followed by a device select code and Read/Write
bit (RW
) (as described in Ta bl e 2), terminated by an acknowledge bit.
When writing data to the memory, the device inserts an acknowledge bit during the 9
th
bit
time, following the bus master’s 8-bit transmission. When data is read by the bus master, the
bus master acknowledges the receipt of the data byte in the same way. Data transfers are
terminated by a Stop condition after an Ack for Write, and after a NoAck for Read.
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