Datasheet

DC and AC parameters M24C64-DF, M24C64-W, M24C64-R, M24C64-F
30/43 Doc ID 16891 Rev 21
Table 17. 1 MHz AC characteristics
(1)
1. Preliminary information, only new M24C64 devices identified by the process letter K are qualified at 1 MHz.
Test conditions specified in Tabl e 7, Ta b le 8 and Ta bl e 1 0
Symbol Alt. Parameter Min. Max. Unit
f
C
f
SCL
Clock frequency 0 1 MHz
t
CHCL
t
HIGH
Clock pulse width high 260 - ns
t
CLCH
t
LOW
Clock pulse width low 400 - ns
t
XH1XH2
t
R
Input signal rise time
(2)
2. There is no min. or max. values for the input signal rise and fall times. It is however recommended by the
I²C specification that the input signal rise and fall times be more than 20 ns and less than 300 ns when
f
C
< 400 kHz, or less than 120 ns when f
C
<1MHz.
(2)
ns
t
XL1XL2
t
F
Input signal fall time
(2) (2)
ns
t
QL1QL2
(6)
t
F
SDA (out) fall time 20
(3)
3. With C
L
= 10 pF
120 ns
t
DXCX
t
SU:DAT
Data in setup time 50 - ns
t
CLDX
t
HD:DAT
Data in hold time 0 - ns
t
CLQX
t
DH
Data out hold time 100 - ns
t
CLQV
(4)(5)
4. To avoid spurious Start and Stop conditions, a minimum delay is placed between SCL=1 and the falling or
rising edge of SDA.
5. t
CLQV
is the time (from the falling edge of SCL) required by the SDA bus line to reach either 0.3 V
CC
or
0.7 V
CC
, assuming that the Rbus × Cbus time constant is within the values specified in Figure 6.
t
AA
Clock low to next data valid (access time) 100 450 ns
t
CHDL
t
SU:STA
Start condition setup time 250 - ns
t
DLCL
t
HD:STA
Start condition hold time 250 - ns
t
CHDH
t
SU:STO
Stop condition setup time 250 - ns
t
DHDL
t
BUF
Time between Stop condition and next Start
condition
500 - ns
t
W
t
WR
Write time - 5 ms
t
NS
(6)
6. Characterized only, not tested in production.
Pulse width ignored (input filter on SCL and
SDA)
-80ns