Datasheet

M24256-BF, M24256-BR, M24256-BW, M24256-DR Signal description
Doc ID 6757 Rev 21 11/42
Figure 7. I
2
C bus protocol
Table 2. Device select code (for memory array)
Device type identifier
(1)
1. The most significant bit, b7, is sent first.
Chip Enable address
(2)
2. E0, E1 and E2 are compared against the respective external pins on the memory device.
RW
b7 b6 b5 b4 b3 b2 b1 b0
Device select code 1010E2E1E0RW
Table 3. Device select code to access the Identification page (M24256-DR only)
Device type identifier
(1)
1. The most significant bit, b7, is sent first.
Chip Enable address
(2)
2. E0, E1 and E2 are compared against the respective external pins on the memory device.
RW
b7 b6 b5 b4 b3 b2 b1 b0
Device select code 1011E2E1E0RW
SCL
SDA
SCL
SDA
SDA
Start
condition
SDA
Input
SDA
Change
AI00792c
Stop
condition
1 23 7 89
MSB
ACK
Start
condition
SCL
1 23 7 89
MSB ACK
Stop
condition