Datasheet

ManualsBrandsST ManualsEEPROMEEPROM 32 k x 8 Bit SO-8

March 2010 Doc ID 6757 Rev 21 1/42

M24256-BF M24256-BR

M24256-BW M24256-DR

256 Kbit serial I²C bus EEPROM

with three Chip Enable lines

Features

■ 256 Kbit EEPROM addressed through the I

bus

■ Supports the I

C bus modes:

– 1 MHz Fast-mode Plus

– 400 kHz Fast mode

– 100 kHz Standard mode

■ Supply voltage ranges:

– 1.7 V to 5.5 V

– 1.8 V to 5.5 V

– 2.5 V to 5.5 V

■ Write Control input

■ Byte and Page Write

■ Random and sequential read modes

■ Self-timed programming cycle

■ Automatic address incrementing

■ Enhanced ESD/latch-up protection

■ More than 1 000 000 write cycles

■ More than 40-year data retention

■ Packages

–ECOPACK

(RoHS compliant)

SO8 (MW)

208 mils width

TSSOP8 (DW)

SO8 (MN)

150 mils width

WLCSP (CS)

UFDFPN8 (MB)

2 × 3 mm (MLP)

www.st.com

Summary of content (42 pages)

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M24256-BF M24256-BR M24256-BW M24256-DR 256 Kbit serial I²C bus EEPROM with three Chip Enable lines Features ■ 256 Kbit EEPROM addressed through the I2C bus ■ Supports the I2C bus modes: – 1 MHz Fast-mode Plus – 400 kHz Fast mode – 100 kHz Standard mode ■ Supply voltage ranges: – 1.7 V to 5.5 V – 1.8 V to 5.5 V – 2.5 V to 5.
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Contents M24256-BF, M24256-BR, M24256-BW, M24256-DR Contents 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 Signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.1 Serial Clock (SCL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.2 Serial Data (SDA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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M24256-BF, M24256-BR, M24256-BW, M24256-DR Contents 3.18 Read Identification Page status (locked/unlocked) . . . . . . . . . . . . . . . . . . 22 3.19 Acknowledge in Read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 4 Initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 6 DC and AC parameters . . . . . .
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List of tables M24256-BF, M24256-BR, M24256-BW, M24256-DR List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. 4/42 Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Device select code (for memory array) . . .
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M24256-BF, M24256-BR, M24256-BW, M24256-DR List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Package connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Description 1 M24256-BF, M24256-BR, M24256-BW, M24256-DR Description The M24256-Bx devices are I2C-compatible electrically erasable programmable memories (EEPROM). They are organized as 32 Kb × 8 bits. The M24256-Bx and M24256-DR can decode the type identifier code (1010) in accordance with the I2C bus definition. The M24256-DR also decodes the type identifier code (1011) when accessing the identification page.
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M24256-BF, M24256-BR, M24256-BW, M24256-DR Figure 2. Description Package connections E0 E1 E2 VSS 8 7 6 5 1 2 3 4 VCC WC SCL SDA AI04035e 1. See Package mechanical data section for package dimensions, and how to identify pin-1. Figure 3.
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Signal description M24256-BF, M24256-BR, M24256-BW, M24256-DR 2 Signal description 2.1 Serial Clock (SCL) This input signal is used to strobe all data in and out of the device. In applications where this signal is used by slave devices to synchronize the bus to a slower clock, the bus master must have an open drain output, and a pull-up resistor must be connected from Serial Clock (SCL) to VCC. (Figure 6 indicates how the value of the pull-up resistor can be calculated).
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M24256-BF, M24256-BR, M24256-BW, M24256-DR 2.5 Signal description VSS ground VSS is the reference for the VCC supply voltage. 2.6 Supply voltage (VCC) 2.6.1 Operating supply voltage VCC Prior to selecting the memory and issuing instructions to it, a valid and stable VCC voltage within the specified [VCC(min), VCC(max)] range must be applied (see Table 8, Table 9 and Table 10).
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Signal description M24256-BF, M24256-BR, M24256-BW, M24256-DR I2C Fast mode (fC = 400 kHz): maximum Rbus value versus bus parasitic capacitance (Cbus) Figure 5. Bus line pull-up resistor (k ) 100 10 4 kΩ When tLOW = 1.3 µs (min value for fC = 400 kHz), the Rbus × Cbus time constant must be below the 400 ns time constant line represented on the left.
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M24256-BF, M24256-BR, M24256-BW, M24256-DR Figure 7. Signal description I2C bus protocol SCL SDA SDA Input Start condition SCL 1 2 SDA MSB SDA Change Stop condition 3 7 8 9 ACK Start condition SCL 1 SDA MSB 2 3 7 8 9 ACK Stop condition AI00792c Table 2. Device select code (for memory array) Device type identifier(1) Device select code Chip Enable address(2) RW b7 b6 b5 b4 b3 b2 b1 b0 1 0 1 0 E2 E1 E0 RW 1. The most significant bit, b7, is sent first. 2.
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Signal description Table 4. b15 Table 5.
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M24256-BF, M24256-BR, M24256-BW, M24256-DR 3 Device operation Device operation The device supports the I2C protocol. This is summarized in Figure 7. Any device that sends data on to the bus is defined to be a transmitter, and any device that reads the data to be a receiver. The device that controls the data transfer is known as the bus master, and the other as the slave device. A data transfer can only be initiated by the bus master, which will also provide the serial clock for synchronization.
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Device operation 3.5 M24256-BF, M24256-BR, M24256-BW, M24256-DR Addressing the memory array To start communication between the bus master and the slave device, the bus master must initiate a Start condition. Following this, the bus master sends the device select code, shown in Table 2 (on Serial Data (SDA), most significant bit first). The device select code consists of a 4-bit device type identifier, and a 3-bit Chip Enable “Address” (E2, E1, E0).
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M24256-BF, M24256-BR, M24256-BW, M24256-DR Figure 8.
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Device operation 3.6 M24256-BF, M24256-BR, M24256-BW, M24256-DR Write operations Following a Start condition the bus master sends a device select code with the Read/Write bit (RW) reset to 0. The device acknowledges this, as shown in Figure 9, and waits for two address bytes. The device responds to each address byte with an acknowledge bit, and then waits for the data byte. Writing to the memory may be inhibited if Write Control (WC) is driven High.
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M24256-BF, M24256-BR, M24256-BW, M24256-DR 3.9 Device operation Identification Page Write (M24256-DR only) The Identification page is written by issuing an ID Write instruction. This instruction uses the same protocol and format as the Page Write in memory array, except for the following differences: ● Device Type Identifier = 1011b ● MSB address bits A15/A6 are don't care except for address bit A10 which must be ‘0’. LSB address bits A5/A0 define the byte address inside the identification page.
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Device operation Figure 9.
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M24256-BF, M24256-BR, M24256-BW, M24256-DR Device operation Figure 10.
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Device operation 3.13 M24256-BF, M24256-BR, M24256-BW, M24256-DR Read operations Read operations are performed independently of the state of the Write Control (WC) signal. After the successful completion of a Read operation, the device’s internal address counter is incremented by one, to point to the next byte address. Figure 11.
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M24256-BF, M24256-BR, M24256-BW, M24256-DR 3.15 Device operation Current Address Read (in memory array) For the Current Address Read operation, following a Start condition, the bus master only sends a device select code with the Read/Write bit (RW) set to 1. The device acknowledges this, and outputs the byte addressed by the internal address counter. The counter is then incremented. The bus master terminates the transfer with a Stop condition, as shown in Figure 11, without acknowledging the byte. 3.
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Device operation 3.18 M24256-BF, M24256-BR, M24256-BW, M24256-DR Read Identification Page status (locked/unlocked) The locked/unlocked status of the Identification page can be checked by issuing a specific truncated instruction consisting of the Identification Page Write instruction followed by one data byte. The data byte will be acknowledged if the Identification page is unlocked, while it will not be acknowledged if the Identification page is locked.
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M24256-BF, M24256-BR, M24256-BW, M24256-DR 4 Initial delivery state Initial delivery state The device is delivered with all bits in the memory array set to 1 (each byte contains FFh). 5 Maximum rating Stressing the device outside the ratings listed in Table 7 may cause permanent damage to the device. These are stress ratings only, and operation of the device at these, or any other conditions outside those indicated in the operating sections of this specification, is not implied.
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DC and AC parameters 6 M24256-BF, M24256-BR, M24256-BW, M24256-DR DC and AC parameters This section summarizes the operating and measurement conditions, and the dc and ac characteristics of the device. The parameters in the DC and AC characteristic tables that follow are derived from tests performed under the measurement conditions summarized in the relevant tables.
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M24256-BF, M24256-BR, M24256-BW, M24256-DR Table 12. Input parameters Parameter(1) Symbol DC and AC parameters Test condition Min. Max. Unit CIN Input capacitance (SDA) 8 pF CIN Input capacitance (other pins) 6 pF ZL(2) Input impedance (E2, E1, E0, WC) VIN < 0.3VCC 30 k ZH(2) Input impedance (E2, E1, E0, WC) VIN > 0.7VCC 500 k 1. Sampled only, not 100% tested. 2. E2,E1,E0: Input impedance when the memory is selected (after a Start condition). Table 13.
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DC and AC parameters Table 14. Symbol M24256-BF, M24256-BR, M24256-BW, M24256-DR DC characteristics (voltage range R) Test conditions (in addition to those in Table 9) Parameter ILI Input leakage current (E1, E2, SCL, SDA) ILO Output leakage current ICC ICC0 Min. Max. Unit VIN = VSS or VCC device in Standby mode ±2 µA SDA in Hi-Z, external voltage applied on SDA: VSS or VCC ±2 µA VCC = 1.8 V, fc= 400 kHz (rise/fall time < 50 ns) 0.8 mA VCC = 2.
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M24256-BF, M24256-BR, M24256-BW, M24256-DR Table 15. DC characteristics (voltage range F)(1) Symbol Test condition (in addition to those in Table 9) Parameter ILI Input leakage current (E1, E2, SCL, SDA) ILO Output leakage current ICC ICC0 DC and AC parameters Supply current (Read) Supply current (Write) Min. Max. Unit VIN = VSS or VCC device in Standby mode ±2 µA SDA in Hi-Z, external voltage applied on SDA: VSS or VCC ±2 µA VCC = 1.7 V, fc= 400 kHz (rise/fall time < 50 ns) 0.
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DC and AC parameters Table 16. M24256-BF, M24256-BR, M24256-BW, M24256-DR 400 kHz AC characteristics Test conditions specified in Table 8, Table 9, Table 10 and Table 11 Max.(1) Unit 400 kHz Alt. fC fSCL Clock frequency tCHCL tHIGH Clock pulse width high 600 ns tCLCH tLOW Clock pulse width low 1300 ns tQL1QL2 (2) tXH1XH2 tF tR Parameter Min.
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M24256-BF, M24256-BR, M24256-BW, M24256-DR Table 17. DC and AC parameters 1 MHz AC characteristics(1) Test conditions specified in Table 9 and Table 11 Symbol Alt. Min.(2) Parameter Max.
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DC and AC parameters M24256-BF, M24256-BR, M24256-BW, M24256-DR Figure 13.
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M24256-BF, M24256-BR, M24256-BW, M24256-DR 7 Package mechanical data Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. Figure 14.
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Package mechanical data M24256-BF, M24256-BR, M24256-BW, M24256-DR Figure 15. SO8N – 8-lead plastic small outline, 150 mils body width, package outline h x 45˚ A2 A c ccc b e 0.25 mm GAUGE PLANE D k 8 E1 E 1 L A1 L1 SO-A 1. Drawing is not to scale. Table 19. SO8N – 8-lead plastic small outline, 150 mils body width, package mechanical data inches(1) millimeters Symbol Typ Min A Max Typ 1.75 Max 0.0689 A1 0.1 A2 1.25 b 0.28 0.48 0.011 0.0189 c 0.17 0.23 0.0067 0.
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M24256-BF, M24256-BR, M24256-BW, M24256-DR Package mechanical data Figure 16. TSSOP8 – 8-lead thin shrink small outline, package outline D 8 5 c E1 1 E 4 α A1 A L A2 L1 CP b e TSSOP8AM 1. Drawing is not to scale. Table 20. TSSOP8 – 8-lead thin shrink small outline, package mechanical data inches(1) millimeters Symbol Typ Min A Max Min 1.200 A1 0.050 0.150 0.800 1.050 b 0.190 c 0.090 A2 Typ 1.000 CP Max 0.0472 0.0020 0.0059 0.0315 0.0413 0.300 0.0075 0.0118 0.
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Package mechanical data M24256-BF, M24256-BR, M24256-BW, M24256-DR Figure 17. UFDFPN8 (MLP8) 8-lead ultra thin fine pitch dual flat package no lead 2 x 3 mm, outline e D b L1 L3 E E2 L A D2 ddd A1 UFDFPN-01 1. Drawing is not to scale. 2. The central pad (the area E2 by D2 in the above illustration) is pulled, internally, to VSS. It must not be allowed to be connected to any other voltage or signal line on the PCB, for example during the soldering process. 3.
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M24256-BF, M24256-BR, M24256-BW, M24256-DR Package mechanical data Figure 18. WLCSP, 0.5 mm pitch, package outline Orientation reference D 2 3 1 A e2 e B C E D B G E e3 F e1 A2 A1 A 1. Drawing is not to scale. Table 22. WLCSP 0.5 mm pitch, package mechanical data(1) Inches(2) Millimeters Symbol Typ Min Max Typ Min Max A 0.60 0.55 0.65 0.0236 0.0217 0.0256 A1 0.245 0.22 0.27 0.0096 0.0087 0.0106 A2 0.355 0.330 0.380 0.0140 0.0130 0.0150 B Ø 0.311 Ø 0.
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Part numbering M24256-BF, M24256-BR, M24256-BW, M24256-DR 8 Part numbering Table 23. Ordering information scheme Example: M24256–B W MW 6 T P /AB Device type M24 = I2C serial access EEPROM Device function 256– = 256 Kbit (32 Kb × 8) Device family B: Without Identification page D: With additional Identification page Operating voltage W = VCC = 2.5 to 5.5 V R = VCC = 1.8 to 5.5 V F = VCC = 1.7 to 5.
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M24256-BF, M24256-BR, M24256-BW, M24256-DR Table 24. Part numbering Available M24256-BR, M24256-BW, M24256-BF products (package, voltage range, temperature grade) M24256-BW 2.5 V to 5.5 V M24256-BR 1.8 V to 5.5 V M24256-BF 1.7 V to 5.5 V SO8N (MN) Range 6, Range 3 Range 6 - SO8W (MW) Range 6 - - TSSOP (DW) Range 6 Range 6 Range 6 WLCSP (CS) - Range 6 - UFDFPN8 (MB) - - Range 6 Package Table 25. Available M24256-DR products (package, voltage range, temperature grade) M24256-DR 1.
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Revision history 9 Revision history Table 26. Date Document revision history Revision Changes 29-Jan-2001 1.1 Lead Soldering Temperature in the Absolute Maximum Ratings table amended Write Cycle Polling Flow Chart using ACK illustration updated LGA8 and SO8(wide) packages added References to PSDIP8 changed to PDIP8, and Package Mechanical data updated 10-Apr-2001 1.2 LGA8 Package Mechanical data and illustration updated SO16 package removed 16-Jul-2001 1.
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M24256-BF, M24256-BR, M24256-BW, M24256-DR Table 26. Date 05-May-2006 16-Oct-2006 02-Jul-2007 16-Oct-2007 Revision history Document revision history (continued) Revision Changes 5 Power On Reset paragraph replaced by Section 2.6: Supply voltage (VCC). Figure 4: Device select code added. ECC (error correction code) and write cycling added and specified at 1 Million cycles. ICC0 added and ICC1 specified over the whole voltage range in Table 13 and Table 14. PDIP8 package removed.
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Revision history Table 26. Date Document revision history (continued) Revision Changes 9 1 MHz frequency introduced (M24512-HR root part number). Section 2.6.3: Device reset modified. Figure 5: I2C Fast mode (fC = 400 kHz): maximum Rbus value versus bus parasitic capacitance (Cbus) modified, Figure 6: I2C Fast mode Plus (fC = 1 MHz): maximum Rbus value versus bus parasitic capacitance (Cbus) added. tNS moved from Table 12 to Table 16. ILO test conditions modified in Table 13.
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M24256-BF, M24256-BR, M24256-BW, M24256-DR Table 26. Revision history Document revision history (continued) Date Revision Changes 16-Jun-2009 15 Part numbers updated in cover page header. 20-Aug-2009 16 IOL added to Table 8: Operating conditions (voltage range W). Note 1and ICC modified in Table 13: DC characteristics (voltage range W); Note and ICC modified in Table 14: DC characteristics (voltage range R); 13-Oct-2009 17 Datasheet split to leave only devices with 256 Kbit capacity.
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M24256-BF, M24256-BR, M24256-BW, M24256-DR Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale.