Datasheet

ManualsBrandsST ManualsIntegrated Circuits (ICs)iNEMO Inertial Module, 3D Digital Accelerometer, Digital, 16bit, LGA

80/114 DocID028475 Rev 7

9.56 FIFO_STATUS4 (3Dh)

FIFO status control register (r). For a proper reading of the register, it is recommended to set

the BDU bit in CTRL3_C (12h) to 1.

Table 145. FIFO_STATUS4 register

Table 146. FIFO_STATUS4 register description

9.57 FIFO_DATA_OUT_L (3Eh)

FIFO data output register (r). For a proper reading of the register, it is recommended to set

the BDU bit in CTRL3_C (12h) to 1.

9.58 FIFO_DATA_OUT_H (3Fh)

FIFO data output register (r). For a proper reading of the register, it is recommended to set

the BDU bit in CTRL3_C (12h) to 1.

000000

FIFO_

PATTERN_9

FIFO_

PATTERN_8

FIFO_

PATTERN_[9:8]

Word of recursive pattern read at the next reading.

Table 147. FIFO_DATA_OUT_L register

DATA_

OUT_

FIFO_L_7

DATA_

OUT_

FIFO_L_6

DATA_

OUT_

FIFO_L_5

DATA_

OUT_

FIFO_L_4

DATA_

OUT_

FIFO_L_3

DATA_

OUT_

FIFO_L_2

DATA_

OUT_

FIFO_L_1

DATA_

OUT_

FIFO_L_0

Table 148. FIFO_DATA_OUT_L register description

DATA_OUT_FIFO_L_[7:0] FIFO data output (first byte)

Table 149. FIFO_DATA_OUT_H register

DATA_

OUT_

FIFO_H_7

DATA_

OUT_

FIFO_H_6

DATA_

OUT_

FIFO_H_5

DATA_

OUT_

FIFO_H_4

DATA_

OUT_

FIFO_H_3

DATA_

OUT_

FIFO_H_2

DATA_

OUT_

FIFO_H_1

DATA_

OUT_

FIFO_H_0

Table 150. FIFO_DATA_OUT_H register description

DATA_OUT_FIFO_H_[7:0] FIFO data output (second byte)