Datasheet

DocID028475 Rev 7 113/114
LSM6DSL Revision history
114
15 Revision history
Table 296. Document revision history
Date Revision Changes
03-May-2017 6
Updated Section 4.4.2: I
2
C - inter-IC control interface (added Table 8: I
2
C master timing
values)
Updated Figure 11 and Figure 13
Updated pin status mode 1 and 2 for pins 10 and 11 as well as adding procedure to
disable pull-ups in Table 18: Internal pin status
Updated bit 0 in CTRL1_XL (10h)
Updated CTRL8_XL (17h)
Updated description of SW_RESET bit in Table 57: CTRL3_C register description
Updated description of X_OFS_USR (73h), Y_OFS_USR (74h), Z_OFS_USR (75h)
Minor textual updates
29-Sep-2017 7
Updated Table 3: Mechanical characteristics
Specified SPI mode 3 in Section 4.4.1: SPI - serial peripheral interface and throughout
Section 6: Digital interfaces