Datasheet

Registers Description LIS2DH
40/49 Doc ID 022516 Rev 1
7.20 INT1_SRC (31h)
Interrupt 1 source register. Read only register.
Reading at this address clears INT1_SRC IA bit (and the interrupt signal on INT 1 pin) and
allows the refreshment of data in the INT1_SRC register if the latched option was chosen.
7.21 INT1_THS (32h)
Table 52. INT1_SRC register
0 IA ZHZLYHYLXHXL
Table 53. INT1_SRC description
IA
Interrupt active. Default value: 0
(0: no interrupt has been generated; 1: one or more interrupts have been generated)
ZH
Z high. Default value: 0
(0: no interrupt, 1: Z High event has occurred)
ZL
Z low. Default value: 0
(0: no interrupt; 1: Z Low event has occurred)
YH
Y high. Default value: 0
(0: no interrupt, 1: Y High event has occurred)
YL
Y low. Default value: 0
(0: no interrupt, 1: Y Low event has occurred)
XH
X high. Default value: 0
(0: no interrupt, 1: X High event has occurred)
XL
X low. Default value: 0
(0: no interrupt, 1: X Low event has occurred)
Table 54. INT1_THS register
0 THS6 THS5 THS4 THS3 THS2 THS1 THS0
Table 55. INT1_THS description
THS6 - THS0
Interrupt 1 threshold. Default value: 000 0000
1LSb = 16mg @FS=2g
1LSb = 32 mg @FS=4g
1LSb = 62 mg @FS=8g
1LSb = 186 mg @FS=16g